Commits · f0ec19944860fb62cf02bfe816417802ad637e13 · Roger Ferrer / llvm-epi · GitLab

Jun 07, 2013
- Fold variable that's only used in assert into the assert. · f0ec1994
  Benjamin Kramer authored Jun 07, 2013
  f0ec1994
- Don't cache the instruction and register info from the TargetMachine, because · 5e7656bf
  Bill Wendling authored Jun 07, 2013
  5e7656bf
- Don't cache the instruction and register info from the TargetMachine, because · ead89ef6
  Bill Wendling authored Jun 07, 2013
  ead89ef6
- Don't cache the instruction and register info from the TargetMachine, because · f5358213
  Bill Wendling authored Jun 07, 2013
  f5358213
- Don't cache the instruction and register info from the TargetMachine, because · 90bee83c
  Bill Wendling authored Jun 07, 2013
  90bee83c
- Don't cache the instruction and register info from the TargetMachine, because · 4a7a408e
  Bill Wendling authored Jun 07, 2013
  4a7a408e
- Don't cache the instruction and register info from the TargetMachine, because · f95178e6
  Bill Wendling authored Jun 07, 2013
  f95178e6
- Don't cache the instruction info and register info objects. · 496dc33b
  Bill Wendling authored Jun 07, 2013
  496dc33b
- ARM sched model: Use the right resources for DIV · c5893da3
  Arnold Schwaighofer authored Jun 07, 2013
  c5893da3
- ARM sched model: Add VFP div instruction on Swift · 5f0a2ce5
  Arnold Schwaighofer authored Jun 07, 2013
  5f0a2ce5
- ARM sched model: Add SIMD/VFP load/store instructions on Swift · a30936a3
  Arnold Schwaighofer authored Jun 07, 2013
  a30936a3
- [Sparc]: Use cmp instruction instead of subcc to compare integers. · dc82ac0d
  Venkatraman Govindaraju authored Jun 07, 2013
  dc82ac0d
- R600: Rewrite an awkward loop in R600MachineScheduler · 0030362e
  Vincent Lejeune authored Jun 06, 2013
  0030362e
Jun 06, 2013
- Revert "ARM sched model: Add SIMD/VFP load/store instructions on Swift" · e5f6a8f6
  Arnold Schwaighofer authored Jun 06, 2013
  e5f6a8f6
- ARM sched model: Add SIMD/VFP load/store instructions on Swift · cfe830dc
  Arnold Schwaighofer authored Jun 06, 2013
  cfe830dc
- ARM sched model: Add integer VFP/SIMD instructions on Swift · eac54473
  Arnold Schwaighofer authored Jun 06, 2013
  eac54473
- ARM sched model: Add integer load/store instructions on Swift · dff8e4c4
  Arnold Schwaighofer authored Jun 06, 2013
  dff8e4c4
- ARM sched model: Add integer arithmetic instructions on Swift · 41a7b068
  Arnold Schwaighofer authored Jun 06, 2013
  41a7b068
- ARM sched model: Cortex A9 - More InstRW sched resources · 57142859
  Arnold Schwaighofer authored Jun 06, 2013
  57142859
- ARM sched model: Add branch thumb instructions · f1395b69
  Arnold Schwaighofer authored Jun 06, 2013
  f1395b69
- ARM sched model: Add branch thumb2 instructions · 10ccc99c
  Arnold Schwaighofer authored Jun 06, 2013
  10ccc99c
- ARM sched model: Add branch instructions · 91d4ee37
  Arnold Schwaighofer authored Jun 06, 2013
  91d4ee37
- ARM sched model: Add preload thumb2 instructions · 57727977
  Arnold Schwaighofer authored Jun 06, 2013
  57727977
- ARM sched model: Add preload instructions · 1b413304
  Arnold Schwaighofer authored Jun 06, 2013
  1b413304
- ARM sched model: Add more ALU and CMP thumb instructions · 654649dd
  Arnold Schwaighofer authored Jun 06, 2013
  654649dd
- ARM sched model: Add more ALU and CMP thumb2 instructions · 972ce477
  Arnold Schwaighofer authored Jun 06, 2013
  972ce477
- R600: Remove leftover code in R600MachineScheduler.cpp · 54476a15
  Vincent Lejeune authored Jun 06, 2013
  54476a15
- Cast to the correct type. Pointer, not reference. · b9121681
  Bill Wendling authored Jun 06, 2013
  b9121681
- R600OptimizeVectorRegisters.cpp: Tweak a warning. [-Wsometimes-uninitialized] · 4a8f0793
  NAKAMURA Takumi authored Jun 06, 2013
  4a8f0793
- R600OptimizeVectorRegisters.cpp: Suppress a warning. [-Wunused-variable] · e5555fc2
  NAKAMURA Takumi authored Jun 06, 2013
  e5555fc2
- Trailing linefeed. · 372574d4
  NAKAMURA Takumi authored Jun 06, 2013
  372574d4
- Cast to the proper type. · e4105768
  Bill Wendling authored Jun 06, 2013
  e4105768
- Cache the TargetLowering info object as a pointer. · f7719085
  Bill Wendling authored Jun 06, 2013
  f7719085
- R600: Replace predicate loop with predicate function · acec99c9
  Tom Stellard authored Jun 05, 2013
  acec99c9
Jun 05, 2013
- R600: Add a pass that merge Vector Register · dec18752
  Vincent Lejeune authored Jun 05, 2013
  dec18752
- R600: Schedule copy from phys register at beginning of block · 4b5b8497
  Vincent Lejeune authored Jun 05, 2013
  4b5b8497
- [mips] brcond + setgt/setugt instruction selection patterns. · da4496c8
  Akira Hatanaka authored Jun 05, 2013
  da4496c8
- [PATCH] Fix VGATHER* operand constraints · 00b20cc9
  Michael Liao authored Jun 05, 2013
  00b20cc9
- ARM sched model: Add more ALU and CMP instructions · 81910d0e
  Arnold Schwaighofer authored Jun 05, 2013
  81910d0e
- ARM sched model: Add divsion, loads, branches, vfp cvt · 2773f1de
  Arnold Schwaighofer authored Jun 05, 2013
  2773f1de