Commits · f251379a91d3731be079b701fda0d3551bb22b4e · Roger Ferrer / llvm-epi · GitLab

Apr 30, 2021
- [AMDGPU] Simplify getWaitStatesSince. NFC. · f251379a
  Jay Foad authored Apr 30, 2021
  
  f251379a
- [InlineCost] Remove visitUnaryInstruction() · a3a798d4
  Arthur Eubanks authored Apr 29, 2021
  a3a798d4
- [AMDGPU] Skip promote-alloca for insertelement/insertvalue users · 544be708
  Christudasan Devadasan authored Apr 30, 2021
  544be708
- [RISCV] Fix StackOffset calculation when using sp to access the fixed stack... · 5603ed60
  luxufan authored Apr 12, 2021
  5603ed60
- [AArch64][GlobalISel] Fix width value for G_SBFX/G_UBFX · d7d85f72
  Brendon Cahoon authored Apr 29, 2021
  d7d85f72
- VirtRegMap: Support partially allocated virtual registers · 55a29c6b
  Matt Arsenault authored Oct 25, 2018
  55a29c6b
- VirtRegMap: Add pass option to not clear virt regs · 1cf3d68f
  Matt Arsenault authored Oct 25, 2018
  1cf3d68f
- [AMDGPU][NFC] Refactor hazard recognition IsHazardFn and IsExpiredFn · 424f1f6f
  Carl Ritson authored Apr 30, 2021
  424f1f6f
- [AMDGPU] Remove dead early-out in GCNHazardRecognizer · 749702fc
  Carl Ritson authored Apr 30, 2021
  749702fc
- [CodeGen] don't emit addrsig symbol if it's used only by metadata · cab48e2f
  Zequan Wu authored Apr 28, 2021
  cab48e2f
- [XCOFF] Handle the case when personality routine is an alias · 7049fbf9
  jasonliu authored Apr 29, 2021
  7049fbf9
Apr 29, 2021
- [GlobalISel][Legalizer] Bump up a smallvector size that was found to be too small. NFC. · fa234057
  Amara Emerson authored Apr 29, 2021
  
  fa234057
- [ORC] JITDylib::addDependencies should be run under the session lock. · aaf026d9
  Lang Hames authored Apr 29, 2021
  
  aaf026d9
- [AArch64][GlobalISel] Simplify out of range rotate amount. · 96ec6d91
  Amara Emerson authored Apr 26, 2021
  96ec6d91
- Revert "Generalize getInvertibleOperand recurrence handling slightly" · a047837b
  Philip Reames authored Apr 29, 2021
  a047837b
- [AMDGPU] Fix v_swap_b32 formation on physical registers · 16d707e6
  Jay Foad authored Apr 29, 2021
  16d707e6
- [COST] Improve shuffle kind detection if shuffle mask is provided. · 12c51f23
  Alexey Bataev authored Apr 29, 2021
  12c51f23
- Revert "[COST] Improve shuffle kind detection if shuffle mask is provided." · 6e859f3c
  Alexey Bataev authored Apr 29, 2021
  6e859f3c
- Basic block sections for functions with implicit-section-name attribute · a6441191
  Sriraman Tallam authored Apr 29, 2021
  a6441191
- [InstCombine] narrow popcount with zext operand · 0f8b6686
  Sanjay Patel authored Apr 29, 2021
  0f8b6686
- Revert "RegAlloc: do not consider liveins to EH-pad successors as liveout." · c1b7460b
  Tim Northover authored Apr 29, 2021
  c1b7460b
- AMDGPU/GlobalISel: Fix selection of image intrinsics with unused return · c34900e1
  Petar Avramovic authored Apr 28, 2021
  c34900e1
- RegAlloc: do not consider liveins to EH-pad successors as liveout. · 438a63e1
  Tim Northover authored Apr 29, 2021
  438a63e1
- [AIX][TLS] Add ASM portion changes to support TLSGD relocations to XCOFF objects · ae3377c5
  Victor Huang authored Apr 28, 2021
  ae3377c5
- [SimplifyCFG] Common code sinking: fix application of profitability check · cc632039
  Roman Lebedev authored Apr 29, 2021
  cc632039
- Revert "[X86] Support AMX fast register allocation" · df323ba4
  Benjamin Kramer authored Apr 29, 2021
  df323ba4
- [ConstantFolding] propagate poison through vector reduction intrinsics · 1089158c
  Sanjay Patel authored Apr 29, 2021
  
  1089158c
- [RISCV] Teach DAG combine to fold (and (select_cc lhs, rhs, cc, -1, c), x) ->... · dcdda2bd
  Craig Topper authored Apr 29, 2021
  dcdda2bd
- [COST] Improve shuffle kind detection if shuffle mask is provided. · 92399322
  Alexey Bataev authored Apr 20, 2021
  92399322
- [ConstantFolding] refactor helper for vector reductions; NFC · 71597d40
  Sanjay Patel authored Apr 29, 2021
  71597d40
- [AsmParser][SystemZ][z/OS] Reject "Dot" as current PC on z/OS · ded0a70a
  Anirudh Prasad authored Apr 29, 2021
  ded0a70a
- [RISCV] Enable SPLAT_VECTOR for fixed vXi64 types on RV32. · 0c330afd
  Craig Topper authored Apr 29, 2021
  0c330afd
- [RISCV] Teach computeKnownBits that vsetvli returns number less than 2^31. · 25391cec
  Craig Topper authored Apr 29, 2021
  25391cec
- Revert "[LV] Calculate max feasible scalable VF." · 51d648c1
  Sander de Smalen authored Apr 29, 2021
  51d648c1
- [LLVM][OpenMP] Adding support for OpenMP sections construct in OpenMPIRBuilder · fbd3548d
  Chirag Khandelwal authored Apr 29, 2021
  fbd3548d
- [VPlan] Add getVPSingleValue helper. · a0e1313c
  Florian Hahn authored Apr 29, 2021
  a0e1313c
- [AArch64][SVE] Use SIMD variant of INSR when scalar is the result of a vector extract · 354604a2
  Bradley Smith authored Apr 23, 2021
  354604a2
- [AArch64][SVE] Convert svdup(vec, SV_VL1, elm) to insertelement(vec, elm, 0) · 89085bcc
  Bradley Smith authored Apr 23, 2021
  89085bcc
- [AArch64][SVE] Move convert.{from,to}.svbool optimization into InstCombine · c8f20ed4
  Bradley Smith authored Apr 26, 2021
  c8f20ed4
- [AMDGPU] Allow buildSpillLoadStore in empty bb · 9569d5ba
  Sebastian Neubauer authored Apr 29, 2021
  9569d5ba