Commits · f269bb7da0162f7171395071a59ec7584318383e · Roger Ferrer / llvm-epi · GitLab

Jun 16, 2020
- [ARM] Fix crash trying to generate i1 immediates · f269bb7d
  David Green authored Jun 16, 2020
  f269bb7d
- Fix comment typo - Uexpected -> Unexpected. NFC. · 9d11822f
  Simon Pilgrim authored Jun 16, 2020
  
  9d11822f
- Silence GCC 7 warning · 503a26d8
  Kristof Beyls authored Jun 16, 2020
  503a26d8
- [ARM][NFC] Explicitly specify the fp16 value type in codegen patterns. · f6189da9
  Alexandros Lamprineas authored Jun 16, 2020
  f6189da9
- [X86][SSE] combineVectorSizedSetCCEquality - remove unused AVX2 MOVMSK path. NFCI. · 379c5b31
  Simon Pilgrim authored Jun 15, 2020
  379c5b31
- [X86][SSE] MatchVectorAllZeroTest - handle OR vector reductions · 057c9c7e
  Simon Pilgrim authored Jun 16, 2020
  057c9c7e
- [X86][SSE] combineVectorSizedSetCCEquality - move single Subtarget.hasAVX()... · 65c3fa84
  Simon Pilgrim authored Jun 15, 2020
  65c3fa84
- [AArch64] Print the immediate operand for SPACE pseudo instruction · a3b5f428
  Fangrui Song authored Jun 15, 2020
  a3b5f428
- [AArch64][GlobalISel] Emit constant pool loads for 64 bit fp immediates. · 1035a416
  Amara Emerson authored Jun 15, 2020
  1035a416
- [X86] Add support for inline assembly 'x' constraint for i128. · 255d5dba
  Craig Topper authored Jun 15, 2020
  255d5dba
- [AMDGPU] make ubsan happy with unsigned left shift · 576fa5a5
  Stanislav Mekhanoshin authored Jun 15, 2020
  576fa5a5
- [AMDGPU] Add gfx1030 target · 9ee272f1
  Stanislav Mekhanoshin authored Jun 15, 2020
  9ee272f1
Jun 15, 2020
- [PPCAsmPrinter] support 'L' output template for memory operands · 2d8e105d
  Nick Desaulniers authored Jun 15, 2020
  2d8e105d
- [AArch64][GlobalISel] Add G_EXT and select ext using it · 3495b884
  Jessica Paquette authored Jun 08, 2020
  3495b884
- [Target/PPC] Fold inside an assertion. · e51e8274
  Davide Italiano authored Jun 15, 2020
  e51e8274
- AMDGPU/GlobalISel: Don't hardcode maximum register size · e07cf923
  Matt Arsenault authored Jun 13, 2020
  e07cf923
- AMDGPU/GlobalISel: Extend load/store workaround to i128 vectors · 1a7f115d
  Matt Arsenault authored Jun 15, 2020
  
  1a7f115d
- [LLVM] Change isa<> to a variadic function template · 72d20b96
  Rahul Joshi authored Jun 15, 2020
  72d20b96
- [Target/PPC] Silence an unused variable warning. NFC. · 5cb44196
  Davide Italiano authored Jun 15, 2020
  
  5cb44196
- Recommit "[X86] Separate imm from relocImm handling." · d72cb4ce
  Craig Topper authored Jun 15, 2020
  d72cb4ce
- [WebAssembly] Adding 64-bit version of R_WASM_MEMORY_ADDR_* relocs · 3b29376e
  Wouter van Oortmerssen authored Jun 05, 2020
  3b29376e
- [X86] Remove printanymem/printopaquemem from the InstPrinters. Just tell... · ad1c46c3
  Craig Topper authored Jun 15, 2020
  ad1c46c3
- [llvm][SVE] IR intrinsics for quadword permutation instructions. · 28a00ac9
  Francesco Petrogalli authored Jun 15, 2020
  28a00ac9
- AMDGPU/GlobalISel: Fix 8-byte aligned, 96-bit scalar loads · 2ca55232
  Matt Arsenault authored May 30, 2020
  2ca55232
- [WebAssembly] Adding 64-bit versions of all load & store ops. · d9e0bbd1
  Wouter van Oortmerssen authored May 18, 2020
  d9e0bbd1
- [X86][SSE] Add LowerVectorAllZero helper for checking if all bits of a vector are zero. · cb8a0ba8
  Simon Pilgrim authored Jun 15, 2020
  cb8a0ba8
- [PowerPC] Do not add the relocation addend to the instruction encoding · 57c9dc05
  Stefan Pintilie authored Jun 15, 2020
  57c9dc05
- [X86][SSE] LowerVectorAllZeroTest - add support for >256-bit vectors · ae33cbc4
  Simon Pilgrim authored Jun 15, 2020
  ae33cbc4
- Revert "[X86] Separate imm from relocImm handling." · f47a7766
  Hans Wennborg authored Jun 15, 2020
  f47a7766
- [X86][SSE] LowerVectorAllZeroTest - remove unnecessary bitcasts · 0b806549
  Simon Pilgrim authored Jun 15, 2020
  0b806549
- [ARM][MachineOutliner] Add LR RegSave mode. · 669066de
  Yvan Roux authored Jun 15, 2020
  669066de
- [AArch64] Fix BTI instruction emission. · b8ae3fdf
  Daniel Kiss authored Jun 15, 2020
  b8ae3fdf
- AMDGPU/GlobalISel: Workaround some load/store type selection patterns · dae9554b
  Matt Arsenault authored Jun 09, 2020
  dae9554b
- [VE] Support relocation information in MC layer · e026f147
  Kazushi (Jam) Marukawa authored Jun 15, 2020
  e026f147
- [CostModel] getCFInstrCost in getUserCost. · 2596da31
  Sam Parker authored Jun 15, 2020
  2596da31
- [NFCI][CostModel] Unify FNeg cost · 321ebfd1
  Sam Parker authored Jun 11, 2020
  321ebfd1
- [IR] Prefer hasFnAttribute() where possible (NFC) · 7cac7e0c
  Nikita Popov authored Jun 14, 2020
  7cac7e0c
- [CostModel] Unify ExtractElement cost. · 51541c06
  Sam Parker authored Jun 15, 2020
  51541c06
- [PowerPC] fma chain break to expose more ILP · bd7096b9
  Chen Zheng authored Jun 14, 2020
  bd7096b9
- [PowerPC] Add some InstAlias for mtspr/mfspr instructions · 74abe500
  Kang Zhang authored Jun 15, 2020
  74abe500