Commits · f3a66ec0bdeeae37c5ec4e5ac04a72bc27711f61 · Roger Ferrer / llvm-epi · GitLab

Feb 03, 2022
- [asan][test] Re-generate asan-check-memaccess-add.ll with update_llc_test_checks.py · f3a66ec0
  Fangrui Song authored Feb 02, 2022
  f3a66ec0
- [mte] fix compiler crash with musttail. · 29f92da5
  Florian Mayer authored Feb 02, 2022
  29f92da5
- AMDGPU: Add second emergency slot for SGPR to vmem for large frames · d6fdbbca
  Matt Arsenault authored Nov 23, 2021
  d6fdbbca
Feb 02, 2022
- [mte] support more complicated lifetimes (e.g. for exceptions). · f7a6c341
  Florian Mayer authored Feb 02, 2022
  f7a6c341
- [x86] add test for 'sbb' false dependency stall; NFC · 0e9a3d36
  Sanjay Patel authored Feb 02, 2022
  
  0e9a3d36
- [mte] work around lifetime issue with setjmp. · 8680d6db
  Florian Mayer authored Feb 01, 2022
  8680d6db
- CodeGen: Use asm register names in warning message · a96dbb90
  Matt Arsenault authored Feb 02, 2022
  a96dbb90
- AMDGPU: Implement isAsmClobberable · 245e25f9
  Matt Arsenault authored Feb 02, 2022
  245e25f9
- [RISCV] Add DAG combines to transform ADD_VL/SUB_VL into widening add/sub. · b73d151a
  Craig Topper authored Feb 02, 2022
  b73d151a
- [AMDGPU] Use new target MMO flag MONoClobber · ddd3807e
  Jay Foad authored Feb 02, 2022
  ddd3807e
- [PowerPC] Scalar IBM MASS library conversion pass · 256d2533
  Masoud Ataei authored Feb 02, 2022
  256d2533
- [SimplifyCFG] Start redesigning `FoldTwoEntryPHINode()`. · 1e353f09
  Roman Lebedev authored Jan 23, 2022
  1e353f09
- [AArch64] Genereate CCMP from And CSel · 0cd80639
  David Green authored Feb 02, 2022
  0cd80639
- [x86] invert a vector select IR canonicalization with a binop identity constant · 6592bcec
  Sanjay Patel authored Feb 02, 2022
  6592bcec
- [AArch64][CodeGen] Always use SVE (when enabled) to lower integer divides · 11cf8077
  David Sherwood authored Jan 19, 2022
  11cf8077
- [VE] Packed v512f32 binop isel and tests · 31cca9e6
  Simon Moll authored Feb 02, 2022
  31cca9e6
- [AVR][NFC] Make atomics tests easier to read · 44ee9864
  Ayke van Laethem authored Jan 23, 2022
  44ee9864
- [AVR] Fix atomicrmw result value · 31666478
  Ayke van Laethem authored Jan 19, 2022
  31666478
- [TableGen][RISCV] Relax a restriction in generating patterns for commutable SDNodes. · 7f6441f9
  Craig Topper authored Feb 01, 2022
  7f6441f9
Feb 01, 2022
- [x86] add tests for fmul/fdiv with identity constant in select arm; NFC · 267400c9
  Sanjay Patel authored Feb 01, 2022
  
  267400c9
- [x86] add more tests for select with identity constant; NFC · 81914722
  Sanjay Patel authored Feb 01, 2022
  81914722
- [AMDGPU] Check atomics aliasing in the clobbering annotation · 79606ee8
  Stanislav Mekhanoshin authored Jan 31, 2022
  79606ee8
- Revert "[DAG] Extend SearchForAndLoads with any_extend handling" · c89cfbd4
  David Green authored Feb 01, 2022
  c89cfbd4
- [AMDGPU] Allow scalar loads after barrier · c2b18a3c
  Stanislav Mekhanoshin authored Jan 27, 2022
  c2b18a3c
- [NFC] These tests require a default target · 7a0cbe11
  Chris Bieneman authored Jan 31, 2022
  7a0cbe11
- [AMDGPU][test] Add dso_local to prevent preemptible alias resolution · 1494d064
  Fangrui Song authored Feb 01, 2022
  
  1494d064
- [AArch64] Add some CCMP testing. NFC · c40744d4
  David Green authored Feb 01, 2022
  
  c40744d4
- [Hexagon] Punt on registers without reaching defs in addr mode opt · c935f6e0
  Krzysztof Parzyszek authored Feb 01, 2022
  c935f6e0
- [RISCV] Fix a vsetvli insertion bug involving loads/stores. · 7eb78107
  Craig Topper authored Feb 01, 2022
  7eb78107
- [AArch64] Add signed version of uaddlv test. NFC · d9b4577c
  David Green authored Feb 01, 2022
  
  d9b4577c
- [PowerPC] Update P10 vector insert patterns to use refactored load/stores, and... · 0d6e6475
  Amy Kwan authored Jan 28, 2022
  0d6e6475
- [AArch64] Do not use ABI alignment for mops.memset.tag · a1dc6d4b
  Nikita Popov authored Feb 01, 2022
  a1dc6d4b
- [CodeGen][AArch64] Fix typo in legalizer-info-validation.mir · d0307622
  Alexander Shaposhnikov authored Feb 01, 2022
  
  d0307622
- [CodeGen][AArch64] Fix typo in arm64-zero-cycle-zeroing.ll · 80c27fbf
  Alexander Shaposhnikov authored Feb 01, 2022
  
  80c27fbf
- [DAG] Make it clear mul(x,x) knownbits bit[1] == 0 check should be for x is undef only · d83a96f5
  Simon Pilgrim authored Feb 01, 2022
  d83a96f5
- [RISCV][3/3] Switch undef -> poison in scalable-vector RVV tests · e9ceeedf
  Fraser Cormack authored Feb 01, 2022
  
  e9ceeedf
- [RISCV][2/3] Switch undef -> poison in fixed-vector RVV tests · 8d1169cf
  Fraser Cormack authored Feb 01, 2022
  
  8d1169cf
- [RISCV][1/3] Switch undef -> poison in VP RVV tests · 414f21ed
  Fraser Cormack authored Feb 01, 2022
  414f21ed
- [AArch64] Regenerate test checks (NFC) · ccda3d4e
  Nikita Popov authored Feb 01, 2022
  ccda3d4e
- [RISCV] Add a test showing an incorrect VSETVLI insertion · b00bce2a
  Fraser Cormack authored Jan 31, 2022
  b00bce2a