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Commits · f4a6dd28b6a801d4c7dd8b8aaa33f54d2258171d

llvm-epi
llvm
test
CodeGen
Mips
and1.ll

Oct 15, 2015
- [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. · 8008de55
  Daniel Sanders authored Oct 15, 2015
  8008de55
Apr 17, 2015
- [opaque pointer type] Add textual IR support for explicit type parameter to the call instruction · 23af6484
  David Blaikie authored Apr 16, 2015
  23af6484
Mar 13, 2015
- [opaque pointer type] Add textual IR support for explicit type parameter to gep operator · f72d05bc
  David Blaikie authored Mar 13, 2015
  f72d05bc
Feb 27, 2015
- [opaque pointer type] Add textual IR support for explicit type parameter to load instruction · a79ac14f
  David Blaikie authored Feb 27, 2015
  a79ac14f
Aug 04, 2012
- 1. Redo mips16 instructions to avoid multiple opcodes for same instruction. · 22bec282
  Akira Hatanaka authored Aug 03, 2012
  22bec282

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