Commits · f53f785a6e80c3cd28dfc306ea06e403d967591e · Roger Ferrer / llvm-epi · GitLab

Dec 12, 2014
- [mips] Support SELECT nodes for targets that don't have conditional-move instructions. · f53f785a
  Vasileios Kalintiris authored Dec 12, 2014
  f53f785a
- [AVX512] Minor fix in lowering pattern for broadcast intrustions. · 4204c1ac
  Robert Khasanov authored Dec 12, 2014
  4204c1ac
- Emit Tag_ABI_FP_16bit_format build attribute. · 1a53996c
  Charlie Turner authored Dec 12, 2014
  1a53996c
- R600: Fix min/max matching problems with unordered compares · 1e3a4ebc
  Matt Arsenault authored Dec 12, 2014
  1e3a4ebc
- R600/SI: fmin/fmax_legacy are not associative · 145d5717
  Matt Arsenault authored Dec 12, 2014
  145d5717
- R600/SI: Don't promote f32 select to i32 · 477b1782
  Matt Arsenault authored Dec 12, 2014
  477b1782
- Add target hook for whether it is profitable to reduce load widths · 810cb629
  Matt Arsenault authored Dec 12, 2014
  810cb629
- remove function names from comments; NFC · 757942a3
  Sanjay Patel authored Dec 11, 2014
  757942a3
- R600/SI: Handle physical registers in getOpRegClass · 102a7040
  Matt Arsenault authored Dec 11, 2014
  102a7040
- R600/SI: Don't verify constant bus usage of flag ops · e368cb37
  Matt Arsenault authored Dec 11, 2014
  e368cb37
- return without temporary; NFC · c694ac55
  Sanjay Patel authored Dec 11, 2014
  c694ac55
- Enable MachineVerifier in debug mode for X86, ARM, AArch64, Mips. · b2f2388a
  Matthias Braun authored Dec 11, 2014
  b2f2388a
- [X86] Add a temporary testcase for PR21876/r223996. · 79c79744
  Ahmed Bougacha authored Dec 11, 2014
  79c79744
Dec 11, 2014
- [PowerPC] Better lowering for add/or of a FrameIndex · b5e9b042
  Hal Finkel authored Dec 11, 2014
  b5e9b042
- R600/SI: Use unordered equal instructions · 58d502f0
  Matt Arsenault authored Dec 11, 2014
  58d502f0
- R600/SI: Make more unordered comparisons legal · 8b989efa
  Matt Arsenault authored Dec 11, 2014
  8b989efa
- R600/SI: Use unordered not equal instructions · 9cded7a7
  Matt Arsenault authored Dec 11, 2014
  9cded7a7
- [CodeGen] Add print and verify pass after each MachineFunctionPass by default · 7e37a5f5
  Matthias Braun authored Dec 11, 2014
  7e37a5f5
- This reverts commit r224043 and r224042. · 01c73610
  Rafael Espindola authored Dec 11, 2014
  01c73610
- Enable machineverifier in debug mode for X86, ARM, AArch64, Mips · 199aeff7
  Matthias Braun authored Dec 11, 2014
  199aeff7
- [CodeGen] Add print and verify pass after each MachineFunctionPass by default · a7c82a9f
  Matthias Braun authored Dec 11, 2014
  a7c82a9f
- [Hexagon] Renaming classes in preparation for replacement. · 150b6b3a
  Colin LeMahieu authored Dec 11, 2014
  150b6b3a
- ARM: convert isTargetIOS checks to isTargetDarwin. · e2c33715
  Tim Northover authored Dec 11, 2014
  e2c33715
- [PowerPC] Implement BuildSDIVPow2, lower i64 pow2 sdiv using sradi · 13d104bf
  Hal Finkel authored Dec 11, 2014
  13d104bf
- [AVX512] Add support for 512b variable bit shift intrinsics. · 5fb084e7
  Cameron McInally authored Dec 11, 2014
  5fb084e7
- [Hexagon] Ading i64 <- i32, i32 sextw pattern. · adab8072
  Colin LeMahieu authored Dec 11, 2014
  adab8072
- [Hexagon] Adding encoding information for sign extend word instruction. · eb52f69f
  Colin LeMahieu authored Dec 11, 2014
  eb52f69f
- AVX-512: Added all forms of COMPRESS instruction · 908dbf48
  Elena Demikhovsky authored Dec 11, 2014
  908dbf48
- [mips][microMIPS] Implement CodeGen support for LI16 instruction. · a330a474
  Jozef Kolek authored Dec 11, 2014
  a330a474
- [X86] When converting movs to pushes, don't assume MOVmi operand is an actual immediate · 11165674
  Michael Kuperstein authored Dec 11, 2014
  11165674
- AVX-512: Fixed a bug in lowering setcc for MVT::i1 type · fc081457
  Elena Demikhovsky authored Dec 11, 2014
  fc081457
- test commit (spelling correction) · fb60e77f
  Kumar Sukhani authored Dec 11, 2014
  fb60e77f
- [X86] Add back AVX2 VR256 PMOVX patterns. · 611a3ef0
  Ahmed Bougacha authored Dec 11, 2014
  611a3ef0
- ARM: correctly expand LDR-lit based globals. · 2ac7e4b3
  Tim Northover authored Dec 10, 2014
  2ac7e4b3
Dec 10, 2014
- [Hexagon] Adding combine ri/ir instructions. · 220adb63
  Colin LeMahieu authored Dec 10, 2014
  220adb63
- [Hexagon] Adding encodings for JR class instructions. Updating complier usages. · db0b13ce
  Colin LeMahieu authored Dec 10, 2014
  db0b13ce
- [AArch64] MachO large code-model: Materialize FP constants in code. · 2326650c
  Juergen Ributzka authored Dec 10, 2014
  2326650c
- R600/SI: Use getTargetConstant in AdjustRegClass · 0c05645b
  Marek Olsak authored Dec 10, 2014
  0c05645b
- [Hexagon] Adding JR class predicated call reg instructions. · 8872d207
  Colin LeMahieu authored Dec 10, 2014
  8872d207
- Match new shuffle codegen for MOVHPD patterns · e20437f9
  Sanjay Patel authored Dec 10, 2014
  e20437f9