Commits · f54dc2384d6962327baf3f8b1735a5d62bdeea7e · Roger Ferrer / llvm-epi · GitLab

Jul 11, 2015
- DAGCombiner: Assume invariant load cannot alias a store · f54dc238
  Matt Arsenault authored Jul 10, 2015
  f54dc238
- [ShrinkWrap][PEI] Do not insert epilogue for unreachable blocks. · 8b984d19
  Quentin Colombet authored Jul 10, 2015
  8b984d19
Jul 10, 2015
- Fix AArch64 prologue for empty frame with dynamic allocas. · 00b30204
  Evgeniy Stepanov authored Jul 10, 2015
  00b30204
- ARMLoadStoreOpt: Merge subs/adds into LDRD/STRD; Factor out common code · d9bd22b2
  Matthias Braun authored Jul 10, 2015
  d9bd22b2
- ComputeKnownBits: be a bit smarter about ADDs · b08ae7af
  Fiona Glaser authored Jul 10, 2015
  b08ae7af
- ARMLoadStoreOptimizer: Create LDRD/STRD on thumb2 · e4ba6b8c
  Matthias Braun authored Jul 10, 2015
  e4ba6b8c
- MIR Serialization: Initial serialization of stack objects. · f6bc8667
  Alex Lorenz authored Jul 10, 2015
  f6bc8667
- ARMLoadStoreOptimizer: Rewrite LDM/STM matching logic. · a4a3182d
  Matthias Braun authored Jul 10, 2015
  a4a3182d
- Actually support volatile memcpys in NVPTX lowering · 5c0039a0
  Eli Bendersky authored Jul 10, 2015
  5c0039a0
- [NVPTX] declare no vector registers · ad85c8c2
  Jingyue Wu authored Jul 10, 2015
  ad85c8c2
- [WinEH] Make sure LSDA tables are 4 byte aligned · 85a2450d
  Reid Kleckner authored Jul 10, 2015
  85a2450d
- [x86] enable machine combiner reassociations for scalar double-precision multiplies · 81beefc5
  Sanjay Patel authored Jul 09, 2015
  81beefc5
- [x86] enable machine combiner reassociations for scalar double-precision adds · ea81edf3
  Sanjay Patel authored Jul 09, 2015
  ea81edf3
- MIR Serialization: Serialize the virtual register definitions. · 28148ba8
  Alex Lorenz authored Jul 09, 2015
  28148ba8
- [WinEH] Give up on using CSRs across 32-bit invokes for now · 8eecb3c1
  Reid Kleckner authored Jul 09, 2015
  8eecb3c1
Jul 09, 2015
- MIR Parser: Report an error when parsing machine function with an empty body. · c8704b02
  Alex Lorenz authored Jul 09, 2015
  c8704b02
- [ImplicitNullChecks] Be smarter in picking the memory op. · b7718454
  Sanjoy Das authored Jul 09, 2015
  b7718454
- MIR Serialization: Serialize the simple MachineFrameInfo attributes. · 60541c1d
  Alex Lorenz authored Jul 09, 2015
  60541c1d
- Allow {e,r}bp as the target of {read,write}_register. · a717f255
  Pat Gavlin authored Jul 09, 2015
  a717f255
- fix an invisible bug when combining repeated FP divisors · e2361d4a
  Sanjay Patel authored Jul 09, 2015
  e2361d4a
- Reapply fixed r241790: Fix shift legalization and lowering for big constants. · d1b818bc
  Pawel Bylica authored Jul 09, 2015
  d1b818bc
- [Hexagon] Add support for atomic RMW operations · feaf7b8d
  Krzysztof Parzyszek authored Jul 09, 2015
  feaf7b8d
- [AArch64] Select SBFIZ or UBFIZ instead of left + right shifts · f40f99e3
  Arnaud A. de Grandmaison authored Jul 09, 2015
  f40f99e3
- Test for 241794 (nest attribute in AArch64) · ce4ccdc2
  Renato Golin authored Jul 09, 2015
  ce4ccdc2
- Revert r241790: Fix shift legalization and lowering for big constants. · 627762fd
  Pawel Bylica authored Jul 09, 2015
  627762fd
- Fix shift legalization and lowering for big constants. · eb122f2b
  Pawel Bylica authored Jul 09, 2015
  eb122f2b
- Extended syntax of vector version of getelementptr instruction. · 37a4da82
  Elena Demikhovsky authored Jul 09, 2015
  37a4da82
- MIR Serialization: Serialize the 'undef' register machine operand flag. · 4d026b89
  Alex Lorenz authored Jul 08, 2015
  4d026b89
- [x86] enable machine combiner reassociations for scalar single-precision multiplies · 093fb170
  Sanjay Patel authored Jul 08, 2015
  093fb170
Jul 08, 2015
- Add tests for the NVPTXLowerAggrCopies pass. · 5c27308a
  Eli Bendersky authored Jul 08, 2015
  5c27308a
- MIR Serialization: Serialize the 'killed' register machine operand flag. · 495ad879
  Alex Lorenz authored Jul 08, 2015
  495ad879
- [X86][SSE] Vector shift test cleanup. NFC. · d865503b
  Simon Pilgrim authored Jul 08, 2015
  d865503b
- [Win64] Only treat some functions as having the Win64 convention · 4f21df2b
  Reid Kleckner authored Jul 08, 2015
  4f21df2b
- MIR Parser: Use source locations for MBB naming errors. · b1f9ce8f
  Alex Lorenz authored Jul 08, 2015
  b1f9ce8f
- [Hexagon] Implement commoning of GetElementPtr instructions · 79b2433e
  Krzysztof Parzyszek authored Jul 08, 2015
  79b2433e
- [SEH] Add missing test case from previous realignment commit · 0a3f5f63
  Reid Kleckner authored Jul 08, 2015
  0a3f5f63
- [SEH] Ensure that empty __except blocks have their own BB · ed012dbf
  Reid Kleckner authored Jul 08, 2015
  ed012dbf
- [SPARC] Cleanup handling of the Y/ASR registers. · f238d176
  James Y Knight authored Jul 08, 2015
  f238d176
- [Hexagon] Generate "insert" instructions more aggressively · 21b53a51
  Krzysztof Parzyszek authored Jul 08, 2015
  21b53a51
- Revert 241681: causes Windows builds to fail · d19b4767
  Krzysztof Parzyszek authored Jul 08, 2015
  d19b4767