Commits · f6a6de288bfb23e45ab2558a9c163132cfe7579a · Roger Ferrer / llvm-epi · GitLab

Oct 15, 2015
- [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. · 8008de55
  Daniel Sanders authored Oct 15, 2015
  8008de55
Feb 27, 2015
- [opaque pointer type] Add textual IR support for explicit type parameter to load instruction · a79ac14f
  David Blaikie authored Feb 27, 2015
  a79ac14f
Oct 12, 2012
- Div, Rem int/unsigned int · cf11c59e
  Reed Kotler authored Oct 12, 2012
  cf11c59e