Commits · f6fb752fe80f05e57b4b6928597d1113a558a7c1 · Roger Ferrer / llvm-epi · GitLab

Oct 26, 2018
- [PowerPC] Fix some missed optimization opportunities in combineSetCC · f6fb752f
  Li Jia He authored Oct 26, 2018
  f6fb752f
- [PowerPC][NFC] Add tests for some missed optimization opportunities in combineSetCC · 95214673
  Li Jia He authored Oct 26, 2018
  95214673
- [PowerPC] Keep vector int to fp conversions in vector domain · 6a74bfba
  Nemanja Ivanovic authored Oct 26, 2018
  6a74bfba
- [Pipeliner] Mark swp-art-deps-rec.ll as REQUIRES: asserts after rL345319 · 5300c2e0
  Fangrui Song authored Oct 26, 2018
  5300c2e0
- Revert "[AArch64] Create proper memoperand for multi-vector stores" · 21beeb29
  Vlad Tsyrklevich authored Oct 26, 2018
  21beeb29
- [SystemZ] Pass the DAG pointer from SystemZAddressingMode::dump(). · e2c5cbc1
  Jonas Paulsson authored Oct 26, 2018
  e2c5cbc1
- Reland "[WebAssembly] LSDA info generation" · 24faf859
  Heejin Ahn authored Oct 25, 2018
  24faf859
- [WebAssembly] Support EH instructions in InstPrinter · 3103d3dc
  Heejin Ahn authored Oct 25, 2018
  3103d3dc
- Fix in MachineOperand::printIRValueReference(). · f213f81d
  Jonas Paulsson authored Oct 25, 2018
  f213f81d
- [AArch64] Implement FP16FML intrinsics · f0923f16
  Bryan Chan authored Oct 25, 2018
  f0923f16
- Address comments · 1d13e6be
  Heejin Ahn authored Oct 25, 2018
  1d13e6be
- [WebAssembly] Error out when block/loop markers mismatch · 1147d914
  Heejin Ahn authored Oct 25, 2018
  1147d914
- [x86] add tests for missed load folding; NFC · c14aafda
  Sanjay Patel authored Oct 25, 2018
  c14aafda
Oct 25, 2018
- [Pipeliner] Ignore Artificial dependences while computing recurrences. · ada0f511
  Sumanth Gundapaneni authored Oct 25, 2018
  ada0f511
- [X86] Change X86 backend to look for 'min-legal-vector-width' attribute... · 813064bf
  Craig Topper authored Oct 25, 2018
  813064bf
- [CodeGen] Remove operands from FENTRY_CALL · 5be9e6de
  Francis Visoiu Mistrih authored Oct 25, 2018
  5be9e6de
- [AArch64] Create proper memoperand for multi-vector stores · 53e869da
  David Greene authored Oct 25, 2018
  53e869da
- [AArch64][GlobalISel] Simplify a legalizer test. NFC. · f28e81f6
  Volkan Keles authored Oct 25, 2018
  f28e81f6
- [WebAssembly] Use target-independent saturating add · 0aad98fd
  Thomas Lively authored Oct 25, 2018
  0aad98fd
- [X86] Add some non-AVX512VL command lines to the *vl-vec-test-testn.ll tests. · 4a825e7b
  Craig Topper authored Oct 25, 2018
  4a825e7b
- [X86] Add KNL command lines to movmsk-cmp.ll. · ce0bc381
  Craig Topper authored Oct 25, 2018
  ce0bc381
- [GlobalISel] LegalizerHelper: Fix the incorrect alignment when splitting... · 60c6affc
  Volkan Keles authored Oct 25, 2018
  60c6affc
- [X86] Remove some uarch tuning flags from KNL that look to have been inherited... · 5d787ac4
  Craig Topper authored Oct 25, 2018
  5d787ac4
- [AArch64][GlobalISel] Fix the LegalityPredicate for lowerIf for G_LOAD/G_STORE · 3a103b1d
  Volkan Keles authored Oct 25, 2018
  3a103b1d
- [ARM] Regenerate vdup tests · 8f11ddc3
  Simon Pilgrim authored Oct 25, 2018
  8f11ddc3
- [AArch64] Add EXT patterns for 64-bit EXT of a subvector of a 128-bit vector · 95886520
  John Brawn authored Oct 25, 2018
  95886520
- [AArch64] Do 64-bit vector move of 0 and -1 by extracting from the 128-bit move · 49e61d90
  John Brawn authored Oct 25, 2018
  49e61d90
- [X86] Fix llc invocation on MIR test case · 7d55dd67
  Francis Visoiu Mistrih authored Oct 25, 2018
  7d55dd67
- [GlobalISel] Use the target preferred type for G_EXTRACT_VECTOR_ELT index. · cbd86d84
  Amara Emerson authored Oct 25, 2018
  cbd86d84
- [TargetLowering] Improve vXi64 UINT_TO_FP vXf64 support (P38226) · 838eb240
  Simon Pilgrim authored Oct 25, 2018
  838eb240
- [DebugInfo][Dexter] Unreachable line stepped onto after SimplifyCFG. · 9a24e1a7
  Carlos Alberto Enciso authored Oct 25, 2018
  9a24e1a7
- [WebAssembly] Set LoadExt and TruncStore actions for SIMD types · 325c9c5e
  Thomas Lively authored Oct 25, 2018
  325c9c5e
- [X86] Adjust MIR test case to pacify machine verifier · a6c66982
  Reid Kleckner authored Oct 24, 2018
  a6c66982
- [X86] Fix pipeline tests when enabling MIR verification, NFC · 24d12c28
  Reid Kleckner authored Oct 24, 2018
  24d12c28
- [WebAssembly] Fix immediate of rethrow when throwing to caller · ac764aa8
  Heejin Ahn authored Oct 24, 2018
  ac764aa8
- [WebAssembly] Retain shuffle types during custom lowering · ed951347
  Thomas Lively authored Oct 24, 2018
  ed951347
- [ELF] Fix large code model MIR verifier errors · 49a24278
  Reid Kleckner authored Oct 24, 2018
  49a24278
- [NFC] Rename minnan and maxnan to minimum and maximum · 30f1d691
  Thomas Lively authored Oct 24, 2018
  30f1d691
- [SelectionDAG] DAG combiner for fminnan and fmaxnan · 43bc4620
  Thomas Lively authored Oct 24, 2018
  43bc4620
Oct 24, 2018
- [X86] Add *SP to tailcall register class to fix verifier error · 9c5bda65
  Reid Kleckner authored Oct 24, 2018
  9c5bda65