Commits · f76884b0d3b96a151d1c631685f9770d45630173 · Roger Ferrer / llvm-epi · GitLab

Dec 03, 2018
- [mips] Fix TestDWARF32Version5Addr8AllForms test failure on MIPS hosts · f76884b0
  Simon Atanasyan authored Dec 03, 2018
  f76884b0
- [Hexagon] Remove unused encodings, NFC · a45a55fc
  Krzysztof Parzyszek authored Dec 03, 2018
  a45a55fc
- [WebAssembly] Enforce assembler emits to streamer in order. · c7b89f0f
  Wouter van Oortmerssen authored Dec 03, 2018
  c7b89f0f
- [Hexagon] Update timing classes · 6290a73f
  Krzysztof Parzyszek authored Dec 03, 2018
  6290a73f
- [Hexagon] Change instruction type field in TSFlags to 7 bits · 1cbc5cd3
  Krzysztof Parzyszek authored Dec 03, 2018
  1cbc5cd3
- [MachineOutliner] Drop candidates that require fixups if it's beneficial · 2accb316
  Jessica Paquette authored Dec 03, 2018
  2accb316
- [Hexagon] Add HasV5 predicate for compatibility with auto-generated files · 71a7f447
  Krzysztof Parzyszek authored Dec 03, 2018
  71a7f447
- [Hexagon] Remove unused operand definitions, NFC · a55515f9
  Krzysztof Parzyszek authored Dec 03, 2018
  a55515f9
- [Hexagon] Some formatting changes, NFC · 7ecc277e
  Krzysztof Parzyszek authored Dec 03, 2018
  7ecc277e
- [X86] Teach LowerMUL/LowerMULH for vXi8 to unpack constant RHS. · 5440b63f
  Craig Topper authored Dec 03, 2018
  5440b63f
- [X86] Add DAG combine to combine a v8i32->v8i16 truncate with a packuswb that... · e35b01f8
  Craig Topper authored Dec 03, 2018
  e35b01f8
- [SystemZ::TTI] Return zero cost for ICmp that becomes Load And Test. · 8ae0f88b
  Jonas Paulsson authored Dec 03, 2018
  8ae0f88b
- [AArch64] Add command-line option for SSBS · a17f8556
  Pablo Barrio authored Dec 03, 2018
  a17f8556
- [AMDGPU] Add sdwa support for ADD|SUB U64 decomposed Pseudos · 16de4fd2
  Ron Lieberman authored Dec 03, 2018
  16de4fd2
- ARM: use target-specific SUBS node when combining cmp with cmov. · 5745b6ac
  Tim Northover authored Dec 03, 2018
  5745b6ac
- [NFC][AArch64] Split out backend features · 3c7d062b
  Diogo N. Sampaio authored Dec 03, 2018
  3c7d062b
- [ARM][MC] Move information about variadic register defs into tablegen · 4cf35b4a
  Oliver Stannard authored Dec 03, 2018
  4cf35b4a
- [ARM][Asm] Debug trace for the processInstruction loop · c588110f
  Oliver Stannard authored Dec 03, 2018
  c588110f
- [ARM] FP16: support vld1.16 for vector loads with post-increment · 5afc957e
  Sjoerd Meijer authored Dec 03, 2018
  5afc957e
- [PowerPC] Fix inconsistent ImmMustBeMultipleOf for same instruction · 51986417
  Kang Zhang authored Dec 03, 2018
  51986417
- [NFC] [PowerPC] add an routine in PPCTargetLowering to determine if a global... · 8b7653db
  QingShan Zhang authored Dec 03, 2018
  8b7653db
Dec 02, 2018
- [X86] Add a DAG combine to turn stores of vXi1 on pre-avx512 targets into a... · 959b415e
  Craig Topper authored Dec 02, 2018
  959b415e
- [X86] Fix bad comment. NFC · 6f54ff57
  Craig Topper authored Dec 02, 2018
  6f54ff57
- [X86] Simplify LowerBITCAST code for v2i32/v4i16/v8i8/i64->mmx/i64/f64 bitcast. · 204e4110
  Craig Topper authored Dec 02, 2018
  204e4110
- [X86] Add custom type legalization for v2i32/v4i16/v8i8->mmx bitcasts to avoid... · 4bb07791
  Craig Topper authored Dec 02, 2018
  4bb07791
- [X86] Custom type legalize v2i32/v4i16/v8i8->i64 bitcasts in 64-bit mode... · ec096a1d
  Craig Topper authored Dec 02, 2018
  ec096a1d
Dec 01, 2018
- [MachineOutliner][AArch64] Improve checks for stack instructions · 9a7103b0
  Jessica Paquette authored Dec 01, 2018
  9a7103b0
- [X86] Don't use zero_extend_vector_inreg for mulhu lowering with sse 4.1 · f4b13927
  Craig Topper authored Dec 01, 2018
  f4b13927
- [AMDGPU] Split 64-Bit XNOR to 64-Bit NOT/XOR · ba559ac0
  Graham Sellers authored Dec 01, 2018
  ba559ac0
- [RISCV] Remove RV64I SLLW/SRLW/SRAW patterns and add new test cases · 757d2962
  Alex Bradbury authored Dec 01, 2018
  757d2962
- [NVPTX] Add lowering of i128 numbers as struct fields · e5664b15
  Artem Belevich authored Dec 01, 2018
  e5664b15
Nov 30, 2018
- AMDGPU: Divergence-driven selection of scalar buffer load intrinsics · a7b00058
  Nicolai Haehnle authored Nov 30, 2018
  a7b00058
- AMDGPU: Fix various issues around the VirtReg2Value mapping · a9cc92c2
  Nicolai Haehnle authored Nov 30, 2018
  a9cc92c2
- [MachineOutliner] Outline both register save calls + no LR save calls together · 1cb18ec4
  Jessica Paquette authored Nov 30, 2018
  1cb18ec4
- AArch64: Don't emit CFI for SCS register in nounwind functions. · 35fcc294
  Peter Collingbourne authored Nov 30, 2018
  35fcc294
- [X86] Change vXi8 MULHU lowering to unpack high and low half of lanes instead... · 4d80f199
  Craig Topper authored Nov 30, 2018
  4d80f199
- [X86] Prefer lowerVectorShuffleAsBitMask over using a avx512 masked operation... · 8191307d
  Craig Topper authored Nov 30, 2018
  8191307d
- [AMDGPU] Disable SReg Global LD/ST, perf regression · f48e43bb
  Ron Lieberman authored Nov 30, 2018
  f48e43bb
- [AMDGPU] Combine DPP mov with use instructions (VOP1/2/3) · 3d9afa27
  Valery Pykhtin authored Nov 30, 2018
  3d9afa27
- [RISCV] Add additional CSR instruction aliases (imm. operands) · 4830fdd2
  Alex Bradbury authored Nov 30, 2018
  4830fdd2