Commits · f7cef7ecad1feed74546718ec9a682302056b331 · Roger Ferrer / llvm-epi · GitLab

Dec 06, 2011
- The compact encoding of the registers are 3-bits each. Make sure we shift the · f7cef7ec
  Bill Wendling authored Dec 06, 2011
  f7cef7ec
- Fix ARM handling of tBcc branch relaxation. · 9105085b
  Jim Grosbach authored Dec 06, 2011
  9105085b
- Use an existing function. · 2608157f
  Jakob Stoklund Olesen authored Dec 06, 2011
  2608157f
- Move target-specific logic out of generic MCAssembler. · 25b63fa1
  Jim Grosbach authored Dec 06, 2011
  25b63fa1
- Expose a switch for the new gcov format. · 72d4d32c
  Nick Lewycky authored Dec 06, 2011
  72d4d32c
- Probably not a good idea to convert a single vector load into a memcpy. We · 8abf65a1
  Chad Rosier authored Dec 06, 2011
  8abf65a1
- Tidy up. Hard tabs. · 46be301c
  Jim Grosbach authored Dec 06, 2011
  46be301c
- Switch MCAssembler to method names starting w/ lower-case. · 18e2fe47
  Jim Grosbach authored Dec 06, 2011
  18e2fe47
- Simple branch relaxation for Thumb2 Bcc instructions. · 34a7c6df
  Jim Grosbach authored Dec 05, 2011
  34a7c6df
- Silence tsan false-positives (tsan can't track things which are only safe due to · 897a57ec
  Nick Lewycky authored Dec 05, 2011
  897a57ec
Dec 05, 2011
- Update comment. · 32775577
  Chad Rosier authored Dec 05, 2011
  32775577
- Make the MemCpyOptimizer a bit more aggressive. I can't think of a scenerio · 19446a07
  Chad Rosier authored Dec 05, 2011
  19446a07
- Tweak ADDrr fix. Bad check for explicit .w · b8c719cc
  Jim Grosbach authored Dec 05, 2011
  b8c719cc
- Thumb2 prefer ADD register encoding T2 to T3 when possible. · e489babf
  Jim Grosbach authored Dec 05, 2011
  e489babf
- Add definitions of 64-bit extract and insert instrucions and make · 20cee2eb
  Akira Hatanaka authored Dec 05, 2011
  20cee2eb
- Split ExtIns into two base classes and have instructions EXT and INS derive from · 9b8ac674
  Akira Hatanaka authored Dec 05, 2011
  9b8ac674
- Thumb2 prefer encoding T3 to T4 for ADD/SUB immediate instructions. · ec9ba982
  Jim Grosbach authored Dec 05, 2011
  ec9ba982
- Have LowerJumpTable support Mips64. Modify 2010-07-20-Switch.ll to test N64 and · 34e3df76
  Akira Hatanaka authored Dec 05, 2011
  34e3df76
- ARM assembly parsing for the rest of the VMUL data type aliases. · fdf9e158
  Jim Grosbach authored Dec 05, 2011
  fdf9e158
- Fix previous commit. Oops. · 9e90c5cd
  Jim Grosbach authored Dec 05, 2011
  9e90c5cd
- Tidy up. No functional change. · 2b37e4fc
  Jim Grosbach authored Dec 05, 2011
  2b37e4fc
- ARM assmebler parsing for two-operand VMUL instructions. · 0a978ef7
  Jim Grosbach authored Dec 05, 2011
  0a978ef7
- enable PPC register scavenging by default (update tests and remove some FIXMEs) · 8f6834df
  Hal Finkel authored Dec 05, 2011
  8f6834df
- don't include CR bit subregs in callee-saved list · 72a26e8b
  Hal Finkel authored Dec 05, 2011
  72a26e8b
- add register pressure for CR regs · b544019a
  Hal Finkel authored Dec 05, 2011
  b544019a
- Add a little heuristic to Value::isUsedInBasicBlock to speed it up for small basic blocks. · 13231037
  Benjamin Kramer authored Dec 05, 2011
  13231037
- Remove some leftover remnants that once tried to create 64-bit MMX PALIGNR instructions. · 51bec1a3
  Craig Topper authored Dec 05, 2011
  51bec1a3
- Clean up and optimizations to the X86 shuffle lowering code. No functional change. · 6a55b1dd
  Craig Topper authored Dec 05, 2011
  6a55b1dd
- · 3924cb02
  Nadav Rotem authored Dec 05, 2011
  3924cb02
Dec 04, 2011
- Add inline subprogram names to the name lookup table since they may · 8dda5d0f
  Eric Christopher authored Dec 04, 2011
  8dda5d0f
- Fix 80-column issues. · 80381f6c
  Bob Wilson authored Dec 04, 2011
  80381f6c
- Emit the ctors in the proper order on ARM/EABI. · 965e0c6d
  Anton Korobeynikov authored Dec 03, 2011
  965e0c6d
Dec 03, 2011
- Sparc CodeGen: Fix AnalyzeBranch for PR 10282. Removing addSuccessor() since · 6dae604f
  Venkatraman Govindaraju authored Dec 03, 2011
  6dae604f
- Simplify code. No functionality change. · 71ba18c1
  Benjamin Kramer authored Dec 03, 2011
  71ba18c1
- Clear the new cache. · bbf3c607
  Benjamin Kramer authored Dec 03, 2011
  bbf3c607
- Add a "seen blocks" cache to LVI to avoid a linear scan over the whole cache... · 36647083
  Benjamin Kramer authored Dec 03, 2011
  36647083
- Check for stack space more intelligently. · 006e43bc
  Sanjoy Das authored Dec 03, 2011
  006e43bc
- Fix a bug in the x86-32 code generated for segmented stacks. · 165ca1d4
  Sanjoy Das authored Dec 03, 2011
  165ca1d4
- Creating multiple JITs on X86 in multiple threads causes multiple writes (of · 8fd1254a
  Nick Lewycky authored Dec 03, 2011
  8fd1254a
- [arm-fast-isel] Unaligned stores of floats require special care. · ec3b77e0
  Chad Rosier authored Dec 03, 2011
  ec3b77e0