Commits · f835fc6f4f58275c1b3d75a1d97bb3d2821c833b · Roger Ferrer / llvm-epi · GitLab

Jan 20, 2014
- Revert r199628: "[AArch64 NEON] Fix a bug caused by undef lane when generating VEXT." · f835fc6f
  Chandler Carruth authored Jan 20, 2014
  f835fc6f
- [AArch64 NEON] Fix a bug caused by undef lane when generating VEXT. · ff42e06e
  Kevin Qin authored Jan 20, 2014
  ff42e06e
- [AArch64 NEON] Accept both #0.0 and #0 for comparing with floating point zero in asm parser. · ef66ff78
  Kevin Qin authored Jan 20, 2014
  ef66ff78
Jan 19, 2014
- Move the retrieval of VT after all of the early exits from PerformOrCombine... · 8347c34e
  Michael Gottesman authored Jan 19, 2014
  8347c34e
- ARM ELF: ensure that the tag types are corrected · 93900055
  Saleem Abdulrasool authored Jan 19, 2014
  93900055
- ARM: update build attributes for ABI r2.09 · 196c3212
  Saleem Abdulrasool authored Jan 19, 2014
  196c3212
- Move ARM build attributes into Support · 278a9f43
  Saleem Abdulrasool authored Jan 19, 2014
  278a9f43
- ARM IAS: remove unnecessary special case · 9dedf642
  Saleem Abdulrasool authored Jan 19, 2014
  9dedf642
Jan 18, 2014
- ARM: Let the assembler reject v5 instructions in v4 mode. · dd39a98b
  Benjamin Kramer authored Jan 18, 2014
  dd39a98b
Jan 17, 2014
- Add two new calling conventions for runtime calls · e6250130
  Juergen Ributzka authored Jan 17, 2014
  e6250130
- [mips][msa] Correct pattern for LSA · b825a634
  Daniel Sanders authored Jan 17, 2014
  b825a634
- [mips] Split IIIdiv int II_DIV, II_DIVU, II_DDIV, and II_DDIVU · c7a9f8d2
  Daniel Sanders authored Jan 17, 2014
  c7a9f8d2
- [mips][sched] Split IIImul and IIImult into subclasses. · e95a137b
  Daniel Sanders authored Jan 17, 2014
  e95a137b
- [mips][sched] Split IIHiLo into II_MFHI_MFLO and II_MTHI_MTLO · 9342557e
  Daniel Sanders authored Jan 17, 2014
  9342557e
- Add MLA alias for ARMv4 support. · afc43a1c
  Renato Golin authored Jan 17, 2014
  afc43a1c
- [AArch64 NEON] Expand vector for UDIV/SDIV/UREM/SREM/FREM as neon doesn't support these operations. · e0faea11
  Kevin Qin authored Jan 17, 2014
  e0faea11
- Switch a few instructions to use RI instead I so they don't require REX_W to... · 80ab268b
  Craig Topper authored Jan 17, 2014
  80ab268b
- Add OpSize16 flags to 32-bit CRC32 instructions so they can be encoded correctly in 16-bit mode. · f124c6a5
  Craig Topper authored Jan 17, 2014
  f124c6a5
- Teach x86 asm parser to handle 'opaque ptr' in Intel syntax. · 2d4b3c97
  Craig Topper authored Jan 17, 2014
  2d4b3c97
- Teach X86 asm parser to understand 'ZMMWORD PTR' in Intel syntax. · 9ac290ad
  Craig Topper authored Jan 17, 2014
  9ac290ad
- Fix intel syntax for 64-bit version of FXSAVE/FXRSTOR to use '64' suffix instead of 'q' · a49c2960
  Craig Topper authored Jan 17, 2014
  a49c2960
- VEX_PREFIX_66 doesn't need to set the hasOpSize flag since VEX instructions... · 5a444969
  Craig Topper authored Jan 17, 2014
  5a444969
- Replace duplicated code with a existing helper function. · 3cbe1606
  Craig Topper authored Jan 17, 2014
  3cbe1606
- [AArch64]Fix the problem can't select f16_to_f32 and f32_to_f16. · 17457a2e
  Hao Liu authored Jan 17, 2014
  17457a2e
- [AArch64 NEON] Custom lower conversion between vector integer and vector... · 212d9b4a
  Kevin Qin authored Jan 17, 2014
  212d9b4a
- [AArch64]Fix the problem can't select concat_vectors of two v1i32 types. · 18d92262
  Hao Liu authored Jan 17, 2014
  18d92262
Jan 16, 2014
- [mips][sched] Removed IIXfer. No instructions use it. · 59f99150
  Daniel Sanders authored Jan 16, 2014
  59f99150
- [mips][sched] Put AND, OR, XOR, MOVT_I, and MOVF_I in the same itinerary class... · 4aefdc7b
  Daniel Sanders authored Jan 16, 2014
  4aefdc7b
- Add an emitRawComment function and use it to simplify some uses of EmitRawText. · 0b694814
  Rafael Espindola authored Jan 16, 2014
  0b694814
- [mips][sched] Split IIseb into II_SEB and II_SEH · 4d20f0c0
  Daniel Sanders authored Jan 16, 2014
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- [mips][sched] Split IILogic into II_AND, II_OR, II_XOR, II_ANDI, II_ORI, II_XORI · 306ef07b
  Daniel Sanders authored Jan 16, 2014
  306ef07b
- [mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU. · 980589a8
  Daniel Sanders authored Jan 16, 2014
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- [mips] Correct itin class for MULT_MM and MULTu_MM to IIImult. · bfe1830a
  Daniel Sanders authored Jan 16, 2014
  bfe1830a
- [mips] IIImult should have an InstrItinData in the generic scheduler. Used the... · 818058b2
  Daniel Sanders authored Jan 16, 2014
  818058b2
- For ARM, fix assertuib failures for some ld/st 3/4 instruction with wirteback. · 4df2363a
  Jiangning Liu authored Jan 16, 2014
  4df2363a
- AVX-512: fixed a compare pattern · d1487261
  Elena Demikhovsky authored Jan 16, 2014
  d1487261
- Copy segment register when optimizing to MOV8ao8/MOV16ao16/MOV32ao32. · a9d2c67c
  Craig Topper authored Jan 16, 2014
  a9d2c67c
- Allow x86 mov instructions to/from memory with absolute address to be encoded... · 35da3d19
  Craig Topper authored Jan 16, 2014
  35da3d19
- CommentColumn is always 40. Simplify. · f69b850d
  Rafael Espindola authored Jan 16, 2014
  f69b850d
- Remove use of OpSize for populating VEX_PP field. A prefix encoding is now... · 8a60fff2
  Craig Topper authored Jan 16, 2014
  8a60fff2