Commits · f88b502d9bc7c2d7db8db340d5b98fc7f46eba9c · Roger Ferrer / llvm-epi · GitLab

Feb 16, 2021
- [FileCollector] Fix that the file system case-sensitivity check was inverted · f88b502d
  Raphael Isemann authored Feb 16, 2021
  f88b502d
- [SampleFDO][NFC] Refactor SampleProfile.cpp · 310b3530
  Rong Xu authored Feb 16, 2021
  310b3530
- Revert "[AArch64][GlobalISel] Fold constants into G_GLOBAL_VALUE" · 962b73dd
  Jessica Paquette authored Feb 16, 2021
  962b73dd
- [DAG] PromoteIntRes_ADDSUBSHLSAT - promote ISD::UADDSAT as clamped add · df45c181
  Simon Pilgrim authored Feb 16, 2021
  df45c181
- [RISCV] Add support for fixed vector mask logic operations. · 07ca13fe
  Craig Topper authored Feb 16, 2021
  07ca13fe
- [SelectionDAG][AArch64] Restrict matchUnaryPredicate to only handle... · 064ada4e
  Craig Topper authored Feb 16, 2021
  064ada4e
- [AArch64] Convert CMP/SELECT sign patterns to OR & ASR. · 211147c5
  Florian Hahn authored Feb 16, 2021
  211147c5
- [coro async] Don't promote allocas to the frame or rewrite swifterror if... · 627cfd43
  Arnold Schwaighofer authored Feb 12, 2021
  627cfd43
- [ARM] Use rGPR for writeback vldrs · 1e007cf4
  David Green authored Feb 16, 2021
  1e007cf4
- AMDGPU: Remove kills following clusters of memory instruction · a7455d7b
  Matt Arsenault authored Feb 14, 2021
  a7455d7b
- [DAG] Fold shuffle(bop(shuffle(x,y),shuffle(z,w)),bop(shuffle(a,b),shuffle(c,d))) · 5dfba562
  Simon Pilgrim authored Feb 16, 2021
  5dfba562
- AMDGPU: Fix debug info handling in post-RA bundler · c320e819
  Matt Arsenault authored Feb 14, 2021
  c320e819
- [NFC][LoopInterchange] Explicitly pass both `InnerLoop` and `OuterLoop` to `processLoop` · 6b612a7b
  Ta-Wei Tu authored Feb 16, 2021
  6b612a7b
- [llvm][Aarch64][SVE] Remove extra fmov instruction with certain literals · e86f9ba1
  David Truby authored Feb 16, 2021
  e86f9ba1
- [VPlan] Remove unused Phi member from VPWidenPHIRecipe (NFC). · f64c6260
  Florian Hahn authored Feb 16, 2021
  f64c6260
- [DAG] Avoid APInt copies by directly using the APInt reference from getAPIntValue. NFCI. · 420420de
  Simon Pilgrim authored Feb 16, 2021
  
  420420de
- [DAG] Use APInt::extractBits instead of lshr().trunc(). NFCI. · dd879f7d
  Simon Pilgrim authored Feb 16, 2021
  dd879f7d
- [SVE] Add support for scalable vectorization of loops with int/fast FP reductions · ba1e150d
  Kerry McLaughlin authored Feb 16, 2021
  ba1e150d
- [RISCV] Fix a crash in fixed-length build_vector lowering · 04977ce5
  Fraser Cormack authored Feb 15, 2021
  04977ce5
- [RISCV] Add patterns for scalable-vector fabs & fcopysign · b8701990
  Fraser Cormack authored Feb 04, 2021
  b8701990
- [SCEVExpander] Migrate costAndCollectOperands to use InstructionCost. · 00fe10c6
  Sander de Smalen authored Feb 16, 2021
  00fe10c6
- [VPlan] Manage scalarized values using VPValues. · 54a14c26
  Florian Hahn authored Feb 16, 2021
  54a14c26
- [NewPM] Introduce (GPU)DivergenceAnalysis in the new pass manager · 11bf7da6
  Sameer Sahasrabuddhe authored Feb 16, 2021
  11bf7da6
- [ObjC][ARC] Do not perform code motion on precise release calls · 32dc79c5
  Akira Hatanaka authored Feb 15, 2021
  32dc79c5
Feb 15, 2021
- [CodeGen] Use range-based for loops (NFC) · 22f00f61
  Kazu Hirata authored Feb 15, 2021
  
  22f00f61
- [RISCV] Add expicit i32/i64 types to RV32 or RV64 only isel patterns. NFC · 29b894a8
  Craig Topper authored Feb 15, 2021
  29b894a8
- GlobalISel: Handle arguments partially passed on the stack · 392e0fcf
  Matt Arsenault authored Feb 07, 2021
  392e0fcf
- CodeGen: Move function to get subregister indexes to cover a LaneMask · 1b3d8dde
  Matt Arsenault authored Dec 01, 2020
  1b3d8dde
- [RISCV] Add support for fixed vector floating point setcc. · 7ba2e1c6
  Craig Topper authored Feb 15, 2021
  7ba2e1c6
- [RISCV][LegalizeTypes] Try to expand BITREVERSE before promoting if the... · eb75f250
  Craig Topper authored Feb 15, 2021
  eb75f250
- [ValueTracking] add scan limit for assumes · 378941f6
  Sanjay Patel authored Feb 15, 2021
  378941f6
- TransformUtils: Fix metadata handling in CloneModule (and improve CloneFunctionInto) · 22a52dfd
  Duncan P. N. Exon Smith authored Feb 11, 2021
  22a52dfd
- [lto] Enable new PM when the PM config is non-empty · 715dc556
  Benjamin Kramer authored Feb 15, 2021
  715dc556
- [AMDGPU] Add two TSFlags: IsAtomicNoRtn and IsAtomicRtn · 5cf9292c
  Stanislav Mekhanoshin authored Feb 12, 2021
  5cf9292c
- Support emitting complex expressions that include entry values · 09b832e7
  Adrian Prantl authored Feb 11, 2021
  09b832e7
- [DAG] visitVSELECT - move OpLHS == LHS into inner if() in USUBSAT matching. NFCI. · e47f21da
  Simon Pilgrim authored Feb 15, 2021
  e47f21da
- [AArch64] Move machine bundle unpacking to PreEmit2 phase. · ca23b2c8
  Florian Hahn authored Feb 15, 2021
  ca23b2c8
- [ARM] Add some basic Min/Max costs · 0a98efb0
  David Green authored Feb 15, 2021
  0a98efb0
- [CostModel]Add cost model for experimental.vector.reverse · b52e6c58
  Caroline Concatto authored Jan 27, 2021
  b52e6c58
- [LoopVectorizer] Require no-signed-zeros-fp-math=true for fmin/fmax · 5fe15934
  Kerry McLaughlin authored Feb 15, 2021
  5fe15934