Commits · f90973f48645d1d1799d7bdb81cd6873e3a8ab71 · Roger Ferrer / llvm-epi · GitLab

Feb 25, 2020
- [NFC][SCEV] Piping to pass TTI into SCEVExpander::isHighCostExpansionHelper() · 0789f280
  Roman Lebedev authored Feb 25, 2020
  0789f280
- [AMDGPU] Implement wave64 DWARF register mapping · 481b1c83
  Scott Linder authored Nov 08, 2019
  481b1c83
- [X86MCTargetDesc.h] Speculative fix for macro collision with sys/param.h · eee22ec3
  Vedant Kumar authored Feb 25, 2020
  eee22ec3
- AMDGPU/GlobalISel: Use packed for G_ADD/G_SUB/G_MUL v2s16 · 86e13ec1
  Matt Arsenault authored Feb 17, 2020
  
  86e13ec1
- AMDGPU/GlobalISel: Legalize s64 min/max by lowering · 33cbd5ee
  Jay Foad authored Feb 25, 2020
  33cbd5ee
- [AArch64][SVE] Update names and comments for gathers/scatters (NFC) · cff90c93
  Andrzej Warzynski authored Feb 19, 2020
  cff90c93
- Don't generate libcalls for wide shift on Windows ARM (PR42711) · decd021f
  Hans Wennborg authored Feb 25, 2020
  decd021f
- [AArch64][SVE] Add predicate reinterpret intrinsics · 72848f26
  Cullen Rhodes authored Feb 11, 2020
  72848f26
- [X86] Pass parameters into selectVectorAddr to remove dependency on X86MaskedGatherScatterSDNode. · 89ba4aca
  Craig Topper authored Feb 24, 2020
  89ba4aca
- [X86] Remove mask output from X86 gather/scatter ISD opcodes. · 9238dfb4
  Craig Topper authored Feb 24, 2020
  9238dfb4
- [Sparc][NFC] Remove trailing space · 84c3d3f3
  Jim Lin authored Feb 25, 2020
  
  84c3d3f3
- AMDGPU/GlobalISel: Introduce post-legalize combiner · fee41517
  Matt Arsenault authored Feb 17, 2020
  fee41517
- AMDGPU/GlobalISel: Fix incorrect VOP3P fneg folding · 0b46b078
  Matt Arsenault authored Feb 19, 2020
  0b46b078
- [AArch64] SVE implies fullfp16 · 248eaff8
  Eli Friedman authored Feb 21, 2020
  248eaff8
- AMDGPU/GlobalISel: Lower 64-bit uaddo/usubo · 0ed4744b
  Jay Foad authored Jan 24, 2020
  0ed4744b
Feb 24, 2020
- [Hexagon] Lower vector predicate store · 820df6e6
  Ikhlas Ajbar authored Jan 28, 2020
  820df6e6
- [Hexagon] Lower bitcast of a vector predicate · a8a4f99a
  Ikhlas Ajbar authored Jan 09, 2020
  a8a4f99a
- [X86] Add back fmaddsub intrinsics to work towards fixing the strict fp implementation · 72732843
  Craig Topper authored Feb 24, 2020
  72732843
- [AMDGPU] use llvm_unreachable instead of default for rp set · 4135077e
  Stanislav Mekhanoshin authored Feb 23, 2020
  4135077e
- [AVR] Disassemble register operands · 5b2046c9
  Ayke van Laethem authored Feb 05, 2020
  5b2046c9
- [X86] combineX86ShuffleChain - select X86ISD::FAND/ISD::AND based on MaskVT · daac8dba
  Simon Pilgrim authored Feb 24, 2020
  daac8dba
- [AVR] Don't assert on an undefined operand · d1af6011
  Ayke van Laethem authored Feb 04, 2020
  d1af6011
- [AVR] Use correct register class for mul instructions · a5424ded
  Ayke van Laethem authored Feb 24, 2020
  a5424ded
- [XCOFF][AIX] Fix incorrect alignment for function descriptor csect · bee70bff
  jasonliu authored Feb 24, 2020
  bee70bff
- [X86] getTargetShuffleInputs - check that the source inputs are all the right size. · 59d8d13c
  Simon Pilgrim authored Feb 24, 2020
  59d8d13c
- [PowerPC][AIX] Spill/restore the callee-saved condition register bits. · 8efc2f57
  Sean Fertile authored Feb 24, 2020
  8efc2f57
- [CostModel][X86] We don't need a scale factor for SLM extract costs · b8243887
  Simon Pilgrim authored Feb 24, 2020
  b8243887
- [MIR][ARM] MachineOperand comments · 7efabe5c
  Sjoerd Meijer authored Feb 24, 2020
  7efabe5c
- [AArch64][SVE] Add the SVE dupq_lane intrinsic · f87f23c8
  Kerry McLaughlin authored Feb 24, 2020
  f87f23c8
- [RDA][ARM][LowOverheadLoops] Iteration count IT blocks · a67eb221
  Sam Parker authored Feb 24, 2020
  a67eb221
- [AArch64][SVE] Add intrinsics for SVE2 cryptographic instructions · f2ff1534
  Kerry McLaughlin authored Feb 24, 2020
  f2ff1534
- [MC] Widen the functional unit type from 32 to 64 bits. · c3f36acc
  Bevin Hansson authored Dec 09, 2019
  c3f36acc
- [ARM][MVE] Combine more extending masked loads · 03756a41
  Sam Parker authored Feb 21, 2020
  03756a41
- [X86] When creating X86ISD::MGATHER nodes from AVX2 gather intrinsics, cast... · 7a7146cf
  Craig Topper authored Feb 23, 2020
  7a7146cf
- [X86] Use custom isel for gather/scatter instructions. · f1b8ec33
  Craig Topper authored Feb 23, 2020
  f1b8ec33
- [NFC][PowerPC] Refactor the tryAndWithMask() · 8b3a62dc
  QingShan Zhang authored Feb 24, 2020
  8b3a62dc
- [X86] Remove most X86 specific subclasses of MemSDNode. Just use a... · 5a705186
  Craig Topper authored Feb 23, 2020
  5a705186
- [X86] Enable the use of movlps for i64 atomic load on 32-bit targets with sse1. · 15b6aa74
  Craig Topper authored Feb 23, 2020
  15b6aa74
- [X86] Use FIST for i64 atomic stores on 32-bit targets without SSE. · 2a10f801
  Craig Topper authored Feb 23, 2020
  
  2a10f801
Feb 23, 2020
- [SystemZ] Support the kernel back chain. · 82879c29
  Jonas Paulsson authored Feb 19, 2020
  82879c29