Commits · f9e872156433419c21219087f627099830024b55 · Roger Ferrer / llvm-epi · GitLab

Oct 08, 2014
- [X86] Avoid generating inc/dec when slow for x.atomic_store(1 + x.atomic_load()) · f9e87215
  Robin Morisset authored Oct 08, 2014
  f9e87215
- [AVX512] Added intrinsics for 128-, 256- and 512-bit versions of VPCMP/VPCMPU{BWDQ} · b51bb226
  Robert Khasanov authored Oct 08, 2014
  b51bb226
- Emit unaligned access build attribute for ARM · 0595a26c
  Renato Golin authored Oct 08, 2014
  0595a26c
- [AArch64] Generate vector signed/unsigned mul and mla/mls long. · d9d0f86a
  Chad Rosier authored Oct 08, 2014
  d9d0f86a
- [X86] Fix a bug with fetch_add(INT32_MIN) · 880580b8
  Robin Morisset authored Oct 07, 2014
  880580b8
Oct 07, 2014
- R600/SI: Remove assertion in SIInstrInfo::areLoadsFromSameBasePtr() · 20fa0be9
  Tom Stellard authored Oct 07, 2014
  20fa0be9
- [mips] Return {f128} correctly for N32/N64. · f3fe49aa
  Daniel Sanders authored Oct 07, 2014
  f3fe49aa
- [FastISel][AArch64] Teach the address computation code to also fold sign-/zero-extends. · ef3722d8
  Juergen Ributzka authored Oct 07, 2014
  ef3722d8
- [FastISel][AArch64] Teach the address computation to also fold sub instructions. · 75b2f340
  Juergen Ributzka authored Oct 07, 2014
  75b2f340
- [FastISel][AArch64] Fix "Fold sign-/zero-extends into the load instruction." · 42bf665f
  Juergen Ributzka authored Oct 07, 2014
  42bf665f
Oct 06, 2014
- [DAGCombine] Remove SIGN_EXTEND-related inf-loop · 98085953
  Hal Finkel authored Oct 06, 2014
  98085953
- Fast-math fold: x / (y * sqrt(z)) -> x * (rsqrt(z) / y) · 7bc9185a
  Sanjay Patel authored Oct 06, 2014
  7bc9185a
- [x86] Remove the 2-addr-to-3-addr "optimization" from shufps to pshufd. · 0927da45
  Chandler Carruth authored Oct 05, 2014
  0927da45
Oct 05, 2014
- [x86, dag] Teach the DAG combiner to prune inputs toa vector_shuffle · daa1ff98
  Chandler Carruth authored Oct 05, 2014
  daa1ff98
- X86: Don't drop half of the mask when converting 2-address shufps into 3-address pshufd. · 77b0e13a
  Benjamin Kramer authored Oct 05, 2014
  77b0e13a
- AVX-512-SKX: Added instruction VPMOVM2B/W/D/Q. · 44bf0637
  Elena Demikhovsky authored Oct 05, 2014
  44bf0637
- [x86] Fix PR21139, one of the last remaining regressions found in the · acecdc02
  Chandler Carruth authored Oct 05, 2014
  acecdc02
- [x86] Teach the new vector shuffle lowering how to lower 128-bit · 9f4d9fa5
  Chandler Carruth authored Oct 05, 2014
  9f4d9fa5
Oct 04, 2014
- [x86] Slap a triple on this test since it is poking around at the stack · 808ec85a
  Chandler Carruth authored Oct 04, 2014
  808ec85a
- [x86] Enable the new vector shuffle lowering by default. · 99627bfb
  Chandler Carruth authored Oct 04, 2014
  99627bfb
- R600/SI: Custom lower f64 -> i64 conversions · c996175b
  Matt Arsenault authored Oct 03, 2014
  c996175b
- R600: Custom lower [s|u]int_to_fp for i64 -> f64 · f7c95e3e
  Matt Arsenault authored Oct 03, 2014
  f7c95e3e
- R600/SI: Fix ftrunc f64 conformance failures. · 6cda8877
  Matt Arsenault authored Oct 03, 2014
  6cda8877
- [x86] Add a really preposterous number of patterns for matching all of · f3e88069
  Chandler Carruth authored Oct 03, 2014
  f3e88069
Oct 03, 2014
- [x86] Adjust the patterns for lowering X86vzmovl nodes which don't · 0adda1e4
  Chandler Carruth authored Oct 03, 2014
  0adda1e4
- Revert "Revert "DI: Fold constant arguments into a single MDString"" · 176b691d
  Duncan P. N. Exon Smith authored Oct 03, 2014
  176b691d
- [ISel] Keep matching state consistent when folding during X86 address match · ff63a2dc
  Adam Nemet authored Oct 03, 2014
  ff63a2dc
- R600: Align functions to 256 bytes · fae1dc8a
  Tom Stellard authored Oct 03, 2014
  fae1dc8a
- [Power] Delete redundant test Atomics-32.ll · 028eabcd
  Robin Morisset authored Oct 03, 2014
  028eabcd
- [Power] Use lwsync for non-seq_cst fences · 9098fee6
  Robin Morisset authored Oct 03, 2014
  9098fee6
- [x86] Teach the new vector shuffle lowering to aggressively form MOVSS · 19640789
  Chandler Carruth authored Oct 03, 2014
  19640789
- Revert 202433 - Provide a target override for the latest regalloc heuristic · 4e31ae10
  Renato Golin authored Oct 03, 2014
  4e31ae10
- [x86] Fix the RUN-lines of this test to make sense. · 7a4459fe
  Chandler Carruth authored Oct 03, 2014
  7a4459fe
- [x86] Significantly improve the ability of the new vector shuffle · 971a560c
  Chandler Carruth authored Oct 03, 2014
  971a560c
- [x86] Add some important, missing test coverage for blending from one · 080cab91
  Chandler Carruth authored Oct 03, 2014
  080cab91
- [x86] Unbreak SSE1 with the new vector shuffle lowering. We can't widen · e91b3162
  Chandler Carruth authored Oct 03, 2014
  e91b3162
- [x86] Add two more triples to stabilize the precise assembly syntax · ea026fbb
  Chandler Carruth authored Oct 03, 2014
  ea026fbb
- [x86] Remove a couple of fairly pointless tests. These were merely · b193d96b
  Chandler Carruth authored Oct 03, 2014
  b193d96b
- [x86] Add another triple to a test to make the comment syntax stable. · 5bacb0ae
  Chandler Carruth authored Oct 03, 2014
  5bacb0ae
- [x86] Add triples to these tests so that we see fewer calling convention · bfde7c2d
  Chandler Carruth authored Oct 03, 2014
  bfde7c2d