Commits · fa5cb4b9366228e8e17a95990a021e62376a592f · Roger Ferrer / llvm-epi · GitLab

Nov 16, 2020
- [LoopFlatten] Disable IV widening · fa5cb4b9
  Sjoerd Meijer authored Nov 16, 2020
  fa5cb4b9
- [AArch64][GlobalISel] Fold G_XOR x, -1 into G_SELECT and select CSINV · 5bc0bd05
  Jessica Paquette authored Nov 13, 2020
  5bc0bd05
- [InferAddrSpace] Teach to handle assumed address space. · f375885a
  Michael Liao authored Nov 07, 2020
  f375885a
- [VE] Add lvm/svm intrinsic instructions · 38621c45
  Kazushi (Jam) Marukawa authored Nov 14, 2020
  38621c45
- [ConstraintElimination] Add support for Or. · 5a4ca8b5
  Florian Hahn authored Nov 16, 2020
  5a4ca8b5
- [LoopVec] Introduce an api for detecting uniform memory ops · 2240d3d0
  Philip Reames authored Nov 16, 2020
  2240d3d0
- [SCEV] Factor out part of wrap flag detection logic [NFC](try 2) · 257d33c8
  Philip Reames authored Nov 16, 2020
  257d33c8
- [coro] Async coroutines: Make sure we can handle control flow in suspend point dispatch function · d861cc0e
  Arnold Schwaighofer authored Nov 16, 2020
  d861cc0e
- [ConstraintElimination] Add complex test cases. · 15beb4e2
  Florian Hahn authored Nov 16, 2020
  
  15beb4e2
- Revert "[InstCombine] add multi-use demanded bits fold for add with low-bit mask" · 4e68bc09
  Sanjay Patel authored Nov 16, 2020
  4e68bc09
- [dsymutil] Generalize handling of aliases external symbols · ee91e231
  Jonas Devlieghere authored Nov 16, 2020
  ee91e231
- [AArch64][GlobalISel] Look through a G_ZEXT when trying to match shift-extended register offsets. · 0b609069
  Amara Emerson authored Nov 13, 2020
  0b609069
- [YAMLIO] Correctly diagnose empty alias/anchor · b877c35d
  Scott Linder authored Nov 16, 2020
  b877c35d
- [RISCV] Add MC tests for the User Vector CSRs · c37cc6bf
  Craig Topper authored Nov 16, 2020
  c37cc6bf
- Reland "[AsmPrinter] fix -disable-debug-info option" · bf6ed355
  Jameson Nash authored Nov 16, 2020
  bf6ed355
- [RISCV] When matching SROIW, check all 64 bits of the OR mask · 124c93c5
  Craig Topper authored Nov 16, 2020
  124c93c5
- [SimplifyCFG] Respect optforfuzzing in NPM pass · aeb0fdff
  Arthur Eubanks authored Nov 13, 2020
  aeb0fdff
- [Coroutine] Allocas used by StoreInst does not always escape · 985c5240
  Xun Li authored Nov 16, 2020
  985c5240
- AMDGPU: Select global saddr mode from SGPR pointer · d2e52eec
  Matt Arsenault authored Nov 10, 2020
  d2e52eec
- [AMDGPU][GlobalISel] Fix lowerShlSat · 4cf6dd51
  Mirko Brkusanin authored Nov 16, 2020
  4cf6dd51
- AMDGPU: Split large offsets when selecting global saddr mode · a6e353b1
  Matt Arsenault authored Nov 09, 2020
  a6e353b1
- Fix the compilation assertion due to unreachable BB pruning not deleting the... · 6bb2ceac
  Victor Huang authored Nov 16, 2020
  6bb2ceac
- [AMDGPU] Add comments. NFC. · a6ecb2eb
  Jay Foad authored Nov 16, 2020
  
  a6ecb2eb
- [VE] Optimize leaf functions · 44a4f939
  Kazushi (Jam) Marukawa authored Nov 15, 2020
  44a4f939
- [MLIR][OpenMP] Add omp.wsloop operation · 84352507
  David Truby authored Nov 16, 2020
  84352507
- [VE] fastcc and vreg-to-vreg copy · a598c08a
  Simon Moll authored Nov 16, 2020
  a598c08a
- BPF: make __builtin_btf_type_id() return 64bit int · 4369223e
  Yonghong Song authored Nov 14, 2020
  4369223e
- [gn build] Port 8dbe44cb · 07927ac6
  LLVM GN Syncbot authored Nov 16, 2020
  
  07927ac6
- Add pass to add !annotate metadata from @llvm.global.annotations. · 8dbe44cb
  Florian Hahn authored Nov 16, 2020
  8dbe44cb
- [VE] Add lsv/lvs intrinsic instructions · 37e7a80a
  Kazushi (Jam) Marukawa authored Nov 14, 2020
  37e7a80a
- [AMDGPU][MC] Corrected error position for some operands and modifiers · 65f3e121
  Dmitry Preobrazhensky authored Nov 16, 2020
  65f3e121
- [Test] More tests on range checks · 58f9ceaa
  Max Kazantsev authored Nov 16, 2020
  
  58f9ceaa
- [AArch64] Add check for widening instruction for SVE. · 6c4d8f46
  Caroline Concatto authored Nov 11, 2020
  6c4d8f46
- [Test] More tests on range check elimination · b2fd9ff5
  Max Kazantsev authored Nov 16, 2020
  
  b2fd9ff5
- [AMDGPU][MC] Corrected error position for swizzle() · 0bee8c78
  Dmitry Preobrazhensky authored Nov 16, 2020
  0bee8c78
- [AMDGPU][MC] Corrected error position for hwreg() and sendmsg() · 89df8fc0
  Dmitry Preobrazhensky authored Nov 16, 2020
  89df8fc0
- [VE] Add pfchv intrinsic instructions · e0c92c6c
  Kazushi (Jam) Marukawa authored Nov 13, 2020
  e0c92c6c
- [LoopFlatten] Fold variable into assert. NFC. · 2e7455f0
  Benjamin Kramer authored Nov 16, 2020
  
  2e7455f0
- [IRGen] Add !annotation metadata for auto-init stores. · ca2e7e59
  Florian Hahn authored Nov 16, 2020
  ca2e7e59
- [LoopFlatten] Widen the IV · 9aa77338
  Sjoerd Meijer authored Nov 09, 2020
  9aa77338