Commits · fa784f63827d046c1dad5cbdf2bb5eabaf456c75 · Roger Ferrer / llvm-epi · GitLab

Apr 07, 2022
- [AArch64] Insert subvector costs · fa784f63
  David Green authored Apr 07, 2022
  fa784f63
- InstCombineCalls: fix annotateAnyAllocCallSite to report changes · f3c702fb
  Augie Fackler authored Apr 06, 2022
  f3c702fb
- [CaptureTracking] Ignore ephemeral values when determining pointer escapeness · 17fdaccc
  Arthur Eubanks authored Apr 05, 2022
  17fdaccc
- MemoryBuiltins: only claim an allocator family on builtin functions · d6a7da5a
  Augie Fackler authored Feb 24, 2022
  d6a7da5a
- BuildLibCalls: also set allocsize() attributes · b9164140
  Augie Fackler authored Feb 10, 2022
  b9164140
- InstCombineCalls: when adding an align attribute, never reduce it · f120be6c
  Augie Fackler authored Mar 14, 2022
  f120be6c
- MemoryBuiltins: also check function definition for allocalign · 5f09498a
  Augie Fackler authored Mar 14, 2022
  5f09498a
- InstCombineCalls: infer return alignment from allocalign attributes · ca051a46
  Augie Fackler authored Apr 04, 2022
  ca051a46
- [x86] Replace getNodeIfExists to doesNodeExist when only check node exist · f72b3a50
  chenglin.bi authored Apr 08, 2022
  f72b3a50
- [RISCV] Add more .vx patterns for VLMax integer setccs. · d98bea87
  Craig Topper authored Apr 07, 2022
  d98bea87
- [RISCV] Add swapped patterns to VPatIntegerSetCCVL_VIPlus1. · 82662b75
  Craig Topper authored Apr 07, 2022
  82662b75
- AMDGPU: Set implicit kernarg size to be of 256 bytes for code object version 5 · 6733590d
  Changpeng Fang authored Apr 07, 2022
  6733590d
- [X86] Enable fast variable per-lane shuffle tuning on all Ryzen targets (PR44795) · cf3a0936
  Simon Pilgrim authored Apr 07, 2022
  cf3a0936
- [Sink] Don't sink non-willreturn calls (PR51188) · e22af03a
  Nikita Popov authored Apr 07, 2022
  e22af03a
- [InstCombine] SimplifyDemandedUseBits - allow and(srem(X,Pow2),C) -> and(X,C)... · afa1ae9e
  Simon Pilgrim authored Apr 07, 2022
  afa1ae9e
- [AMDGPU][MC][GFX10] Added syntactic sugar for s_waitcnt_depctr operand · 1f6aa903
  Dmitry Preobrazhensky authored Apr 07, 2022
  1f6aa903
- remove dead code in parseRegisterList checking for ARM::RA_AUTH_CODE · edeceb86
  Ties Stuij authored Apr 07, 2022
  edeceb86
- [InstCombine] SimplifyDemandedUseBits - add TODO to remove shl node if we only... · 5909c678
  Simon Pilgrim authored Apr 07, 2022
  5909c678
- [InstCombine] SimplifyDemandedUseBits - remove lshr node if we only demand known sign bit · 5e902248
  Simon Pilgrim authored Apr 07, 2022
  5e902248
- [X86] Ensure ZN3Tuning inherits from ZN2Tuning instead of ZNTuning · a1df2ef5
  Simon Pilgrim authored Apr 07, 2022
  a1df2ef5
- [LoongArch] Split asmstr to opcstr and opnstr in LAInst class definition. NFC · ca3c746b
  Weining Lu authored Apr 07, 2022
  ca3c746b
- [RISCV] Fix crash for section alignment with .option norvc · d09d297c
  Luís Marques authored Apr 07, 2022
  d09d297c
- [DebugInfo] Use DW_ATE_signed encoding when creating a Fortran · c226a5c4
  Chih-Ping Chen authored Mar 28, 2022
  c226a5c4
- [CSKY] Support bitcast operation from/to double to/from two GPRs · cfcac264
  Zi Xuan Wu authored Apr 07, 2022
  cfcac264
- [LoongArch] Improve td files indentation a little bit. NFC · 5b32102c
  Weining Lu authored Apr 07, 2022
  
  5b32102c
- [RISCV] Select unmasked integer setcc insts via ISel post-process · 8ebc9b15
  Fraser Cormack authored Apr 06, 2022
  8ebc9b15
- Transforms: Remove unused include · ff485d72
  Benjamin Kramer authored Apr 07, 2022
  ff485d72
- [VPlan] Use vector.body as header name in VPlan native path. · 4388c979
  Florian Hahn authored Apr 07, 2022
  4388c979
- [RISCV][VP] Add basic RVV codegen for vp.fcmp · 8216255c
  Fraser Cormack authored Apr 04, 2022
  8216255c
- [x86] Improve select lowering for smin(x, 0) & smax(x, 0) · 842d0bf9
  Wei Xiao authored Apr 05, 2022
  842d0bf9
- [LoopSink] Use MemorySSA with legacy pass manager · 674ee4d3
  Nikita Popov authored Apr 06, 2022
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- [RISCV] Add CMOV isel pattern for (select (setgt X, Imm), Y, Z) · f8911235
  Liqin Weng authored Apr 07, 2022
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- [CSKY] Fix some Clang warnings. NFC · ef437a7d
  Fangrui Song authored Apr 06, 2022
  ef437a7d
- AMDGPU: Handle private atomics · e6012c8e
  Matt Arsenault authored Apr 05, 2022
  e6012c8e
- AtomicExpand: Add NotAtomic lowering strategy · 7f14a1d4
  Matt Arsenault authored Apr 05, 2022
  7f14a1d4
- AtomicExpand: Change return type for shouldExpandAtomicStoreInIR · c4ea925f
  Matt Arsenault authored Apr 05, 2022
  c4ea925f
- [RISCV] Supplement patterns for vnsrl.wx/vnsra.wx when splat shift is sext or zext · 1b547799
  Lian Wang authored Mar 31, 2022
  1b547799
- [AMDGPU] Check SI LDS offset bug in the allowsMisalignedMemoryAccesses · a41a676e
  Stanislav Mekhanoshin authored Apr 06, 2022
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- Transforms: Split LowerAtomics into separate Utils and pass · 39f15686
  Matt Arsenault authored Apr 05, 2022
  39f15686
- [MIPS] Initial support for MIPS-I load delay slots · 303c1801
  Simon Dardis authored Apr 07, 2022
  303c1801