Commits · fac9941e57013127593a47e02e7e88f56c9be2a4 · Roger Ferrer / llvm-epi · GitLab

Jan 23, 2020
- AMDGPU: Fix ubsan error · fac9941e
  Matt Arsenault authored Jan 23, 2020
  fac9941e
- [SVE] Add SVE2 patterns for unpredicated multiply instructions · 58ceb81d
  Danilo Carvalho Grael authored Jan 15, 2020
  58ceb81d
- [X86] LowerRotate - early out for vector rotates by zero · 0ec25a03
  Simon Pilgrim authored Jan 23, 2020
  
  0ec25a03
- AMDGPU/GlobalISel: Select V_ADD3_U32/V_XOR3_B32 · 618fa77a
  Matt Arsenault authored Jan 21, 2020
  618fa77a
- [Alignment][NFC] Use Align with CreateAlignedStore · 59f95222
  Guillaume Chatelet authored Jan 23, 2020
  59f95222
- AMDGPU: Check for other uses when looking through casted select · dfec7022
  Matt Arsenault authored Jan 23, 2020
  dfec7022
- [Hexagon] Remove unused operand definitions: s10_0Imm and s10_6Imm · cc4b716a
  Krzysztof Parzyszek authored Jan 23, 2020
  
  cc4b716a
- [VE] add, sub, left/right shift isel patterns · 784204fd
  Kazushi (Jam) Marukawa authored Jan 23, 2020
  784204fd
- [VE][NFC] re-write RR* isel class using null_frag · 9187073f
  Simon Moll authored Jan 23, 2020
  9187073f
- [CodeGen] Make use of MachineInstrBuilder::getReg · b482e1bf
  Jay Foad authored Jan 23, 2020
  b482e1bf
- [Alignement][NFC] Deprecate untyped CreateAlignedLoad · 279fa8e0
  Guillaume Chatelet authored Jan 23, 2020
  279fa8e0
- [AArch64][SVE] Add first-faulting load intrinsic · aa0f37e1
  Kerry McLaughlin authored Jan 23, 2020
  aa0f37e1
- [ARM,MVE] Support immediate vbicq,vorrq,vmvnq intrinsics. · 4321c6af
  Simon Tatham authored Jan 23, 2020
  4321c6af
- [ARM,MVE] Revise immediate VBIC/VORR to look more like NEON. · 772e4931
  Simon Tatham authored Jan 23, 2020
  772e4931
- AMDGPU/GlobalISel: Remove redundant or patterns · 4d14772f
  Matt Arsenault authored Jan 22, 2020
  4d14772f
- [RISCV] Fix evaluating %pcrel_lo against global and weak symbols · 3f5976c9
  James Clarke authored Jan 23, 2020
  3f5976c9
- [AArch64TTI] AArch64 supports NT vector stores through STNP. · 39ae86ab
  Florian Hahn authored Jan 22, 2020
  39ae86ab
Jan 22, 2020
- [PowerPC] Collect some CallLowering arguments into a struct. [NFC] · 9aa816a8
  Sean Fertile authored Jan 21, 2020
  9aa816a8
- [x86] fold vperm2x128 to concat of 128-bit high half vectors · 363d27c8
  Sanjay Patel authored Jan 22, 2020
  363d27c8
- AMDGPU/R600: Emit rodata in text segment · 1b8eab17
  Jan Vesely authored Jan 19, 2020
  1b8eab17
- [X86][SSE] combineExtractWithShuffle - extract(bitcast(broadcast(x))) --> x · 5340434c
  Simon Pilgrim authored Jan 22, 2020
  5340434c
- [ARM] Mark MVE loads/store as not having side effects · 58991ba7
  David Green authored Jan 22, 2020
  58991ba7
- Revert "[DA][TTI][AMDGPU] Add option to select GPUDA with TTI" · cd470717
  Nico Weber authored Jan 22, 2020
  cd470717
- [AArch64] Don't rename registers with pseudo defs in Ld/St opt. · 300997c4
  Florian Hahn authored Jan 22, 2020
  300997c4
- AMDGPU/GlobalISel: Handle 16-bank LDS llvm.amdgcn.interp.p1.f16 · 1192d7b2
  Matt Arsenault authored Jan 12, 2020
  1192d7b2
- [NFC][XCOFF] Refactor Csect creation into TargetLoweringObjectFile · 45a4aaea
  David Tenty authored Jan 22, 2020
  45a4aaea
- AMDGPU/GlobalISel: Select llvm.amdgcn.mov.dpp · c05f23e4
  Matt Arsenault authored Jan 17, 2020
  c05f23e4
- AMDGPU/GlobalISel: Select llvm.amdgcn.mov.dpp8 · dd09ec12
  Matt Arsenault authored Jan 17, 2020
  
  dd09ec12
- AMDGPU: Fix element size assertion · 0bf434cc
  Matt Arsenault authored Jan 22, 2020
  0bf434cc
- AMDGPU/GlobalISel: Keep G_BITCAST out of waterfall loop · bb562d1a
  Matt Arsenault authored Jan 04, 2020
  bb562d1a
- [RISCV] Support ABI checking with per function target-features · 0cb274de
  Zakk Chen authored Nov 28, 2019
  0cb274de
- [X86][SSE] combineExtractWithShuffle - extract(bictcast(scalar_to_vector(x))) --> x · a14aa7da
  Simon Pilgrim authored Jan 22, 2020
  a14aa7da
- AMDGPU/GlobalISel: Fold add of constant into G_INSERT_VECTOR_ELT · 52ec7379
  Matt Arsenault authored Jan 03, 2020
  52ec7379
- AMDGPU/GlobalISel: Select G_INSERT_VECTOR_ELT · d1dbb5e4
  Matt Arsenault authored Jan 03, 2020
  
  d1dbb5e4
- AMDGPU/GlobalISel: Fix RegBankSelect for G_INSERT_VECTOR_ELT · 3524d441
  Matt Arsenault authored Jan 03, 2020
  3524d441
- AMDGPU/GlobalISel: Fold constant offset vector extract indexes · e3d352c5
  Matt Arsenault authored Jan 03, 2020
  e3d352c5
- [VE] select and selectcc patterns · 83b67526
  Kazushi (Jam) Marukawa authored Jan 22, 2020
  83b67526
- AMDGPU: Fix typo · e93e1b62
  Matt Arsenault authored Jan 22, 2020
  
  e93e1b62
- AMDGPU: Look through casted selects to constant fold bin ops · 2fe500ab
  Matt Arsenault authored Jan 20, 2020
  2fe500ab
- AMDGPU: Do binop of select of constant fold in AMDGPUCodeGenPrepare · bcd91778
  Matt Arsenault authored Jan 19, 2020
  bcd91778