Commits · fb51e64eaccb49199f06982f4170b160c5737420 · Roger Ferrer / llvm-epi · GitLab

Sep 16, 2019
- AMDGPU/GlobalISel: Fail select of G_INSERT non-32-bit source · fb51e64e
  Matt Arsenault authored Sep 16, 2019
  fb51e64e
- AMDGPU/GlobalISel: Fix RegBankSelect for G_FRINT and G_FCEIL · 1fc07d66
  Matt Arsenault authored Sep 16, 2019
  1fc07d66
- [X86][NFC] Add a `use-aa` feature. · 44bfbcc2
  Clement Courbet authored Sep 16, 2019
  44bfbcc2
- [ARM] Fold VCMP into VPT · ce7328cb
  David Green authored Sep 16, 2019
  ce7328cb
- [SVE][Inline-Asm] Add constraints for SVE predicate registers · e55b3bf4
  Kerry McLaughlin authored Sep 16, 2019
  e55b3bf4
- [AArch64] Some more FP16 FMA pattern matching · b1e1a26e
  Sjoerd Meijer authored Sep 16, 2019
  b1e1a26e
- [SystemZ] Merge the SystemZExpandPseudo pass into SystemZPostRewrite. · ca5acf5b
  Jonas Paulsson authored Sep 16, 2019
  ca5acf5b
- AMDGPU/GlobalISel: Select SMRD loads for more types · bc8de8a8
  Matt Arsenault authored Sep 16, 2019
  bc8de8a8
- AMDGPU/GlobalISel: RegBankSelect for kill · 48b158ac
  Matt Arsenault authored Sep 16, 2019
  48b158ac
- AMDGPU/GlobalISel: Legalize s1 source G_[SU]ITOFP · 01c7f40d
  Matt Arsenault authored Sep 16, 2019
  01c7f40d
- AMDGPU/GlobalISel: Set type on vgpr live in special arguments · 60169ed6
  Matt Arsenault authored Sep 16, 2019
  60169ed6
- AMDGPU/GlobalISel: Select S16->S32 fptoint · 9f52c1ea
  Matt Arsenault authored Sep 16, 2019
  9f52c1ea
- AMDGPU/GlobalISel: Select s32->s16 G_[US]ITOFP · 0a612359
  Matt Arsenault authored Sep 16, 2019
  0a612359
- AMDGPU/GlobalISel: Fix VALU s16 fneg · f5d5cd20
  Matt Arsenault authored Sep 16, 2019
  f5d5cd20
Sep 15, 2019
- [ARM] Masked loads and stores · b325c057
  David Green authored Sep 15, 2019
  b325c057
Sep 14, 2019
- [WebAssembly] Narrowing and widening SIMD ops · ae530c5c
  Thomas Lively authored Sep 13, 2019
  ae530c5c
Sep 13, 2019
- [AArch64][GlobalISel] Tail call memory intrinsics · 727328ab
  Jessica Paquette authored Sep 13, 2019
  727328ab
- [aarch64] move custom isel of extract_vector_elt to td file - NFC · d93e136b
  Sebastian Pop authored Sep 13, 2019
  d93e136b
- AArch64: fix EXPENSIVE_CHECKS for arm64_32. · 52a89cc0
  Tim Northover authored Sep 13, 2019
  52a89cc0
- Revert for: [AMDGPU]: PHI Elimination hooks added for custom COPY insertion. · 9ff70132
  Alexander Timofeev authored Sep 13, 2019
  9ff70132
- [AArch64][GlobalISel] Add support for sibcalling callees with varargs · 14bfb56b
  Jessica Paquette authored Sep 13, 2019
  14bfb56b
- [X86] Use incDecVectorConstant to simplify the min/max code in LowerVSETCC. · 8e0f1049
  Craig Topper authored Sep 13, 2019
  8e0f1049
- [X86] negateFMAOpcode - extend to support FMADDSUB/FMSUBADD and output negation. NFCI. · 930ebc15
  Simon Pilgrim authored Sep 13, 2019
  930ebc15
- [ARM] Add earlyclobber for cross beat MVE instructions · b7b7f262
  David Green authored Sep 13, 2019
  b7b7f262
- [Alignment] Introduce llvm::Align to MCSection · 36202635
  Guillaume Chatelet authored Sep 13, 2019
  36202635
- [ARM] Add support for MVE vmaxv and vminv · 1572b685
  Sam Tebbs authored Sep 13, 2019
  1572b685
- [AArch64] MachineCombiner FMA matching. NFC. · 395a8673
  Sjoerd Meijer authored Sep 13, 2019
  395a8673
- AMDGPU/GlobalISel: Fix assert on multi-return side effect intrinsics · 3b7ffc6a
  Matt Arsenault authored Sep 13, 2019
  3b7ffc6a
- AMDGPU/GlobalISel: Legalize s32->s16 G_SITOFP/G_UITOFP · a4be3eff
  Matt Arsenault authored Sep 13, 2019
  a4be3eff
- [RISCV] Support stack offset exceed 32-bit for RV64 · a49a16dd
  Shiva Chen authored Sep 13, 2019
  a49a16dd
- Revert "[RISCV] Support stack offset exceed 32-bit for RV64" · ea530ba3
  Shiva Chen authored Sep 13, 2019
  ea530ba3
- AMDGPU/GlobalISel: Fix RegBankSelect for amdgcn.else · 67d9349d
  Matt Arsenault authored Sep 13, 2019
  67d9349d
- AMDGPU/GlobalISel: Select 16-bit VALU bit ops · 638f8023
  Matt Arsenault authored Sep 13, 2019
  638f8023
- [RISCV] Support stack offset exceed 32-bit for RV64 · eaa230fe
  Shiva Chen authored Sep 13, 2019
  eaa230fe
- AMDGPU/GlobalISel: Legalize G_FFLOOR · f457dd2b
  Matt Arsenault authored Sep 13, 2019
  f457dd2b
- AMDGPU/GlobalISel: Legalize G_FMAD · 4d339180
  Matt Arsenault authored Sep 13, 2019
  4d339180
- AMDGPU/GlobalISel: Select G_CTPOP · 4a73c6ea
  Matt Arsenault authored Sep 13, 2019
  4a73c6ea
- DAG/GlobalISel: Correct type profile of bitcount ops · b366329a
  Matt Arsenault authored Sep 13, 2019
  b366329a
- AMDGPU: Inline constant when materalizing FI with add on gfx9 · 8382ce5f
  Matt Arsenault authored Sep 12, 2019
  8382ce5f
- Rename nonvolatile_load/store to simple_load/store [NFC] · 0b4d67ca
  Philip Reames authored Sep 12, 2019
  0b4d67ca