Commits · fb5af8b9b93cb270fda7832e24cab9cb62dec16f · Roger Ferrer / llvm-epi · GitLab

Oct 04, 2019
- [MachineOutliner] Disable outlining from noreturn functions · 784892c9
  Jessica Paquette authored Oct 04, 2019
  784892c9
- [ScheduleDAG] When a node is cloned, add an edge between the nodes. · 23ae13d5
  Eli Friedman authored Oct 04, 2019
  23ae13d5
- [X86] Remove isel patterns for mask vpcmpgt/vpcmpeq. Switch vpcmp to these... · 87aa59a0
  Craig Topper authored Oct 04, 2019
  87aa59a0
- [X86] Add DAG combine to form saturating VTRUNCUS/VTRUNCS from VTRUNC · 074fa390
  Craig Topper authored Oct 04, 2019
  074fa390
- [FPEnv] Strict FP tests should use the requisite function attributes. · 68b80521
  Kevin P. Neal authored Oct 04, 2019
  68b80521
- ARM-Darwin: keep the frame register reserved even if not updated. · a7d90af1
  Tim Northover authored Oct 04, 2019
  a7d90af1
- AMDGPU/GlobalISel: Fix using wrong addrspace for aperture · d7cad4fb
  Matt Arsenault authored Oct 04, 2019
  d7cad4fb
- AMDGPU/GlobalISel: Select G_PTRTOINT · 412e0bf8
  Matt Arsenault authored Oct 04, 2019
  412e0bf8
- AMDGPU/GlobalISel: Support wave32 waterfall loops · be9521ac
  Matt Arsenault authored Oct 04, 2019
  be9521ac
- [X86] Enable inline memcmp() to use AVX512 · 03b216d8
  David Zarzycki authored Oct 04, 2019
  03b216d8
- [RISCV] Split SP adjustment to reduce the offset of callee saved register spill and restore · ff55e2e0
  Shiva Chen authored Oct 04, 2019
  ff55e2e0
Oct 03, 2019
- [DAGCombiner] add operation legality checks before creating shift ops (PR43542) · 288079aa
  Sanjay Patel authored Oct 03, 2019
  288079aa
- [Tests] Add a unordered atomic load combine test · 82cb5bc3
  Philip Reames authored Oct 03, 2019
  82cb5bc3
- [Test] Fix inconsistency in alignment in test case · 65d63ac0
  Philip Reames authored Oct 03, 2019
  65d63ac0
- [AArch64][SVE] Move the testcase into CodeGen dir · 230cf9a3
  Jinsong Ji authored Oct 03, 2019
  230cf9a3
- [PowerPC] Adjust the naming and operand order of fnmsub patterns · 4a6881ea
  Jinsong Ji authored Oct 03, 2019
  4a6881ea
- [X86] Add v32i8 shuffle lowering strategy to recognize two v4i64 vectors... · 185ee6ec
  Craig Topper authored Oct 03, 2019
  185ee6ec
- AMDGPU/GlobalISel: Handle RegBankSelect of G_INSERT_VECTOR_ELT · ed77b274
  Matt Arsenault authored Oct 03, 2019
  ed77b274
- AMDGPU/GlobalISel: Split 64-bit vector extracts during RegBankSelect · 233ff982
  Matt Arsenault authored Oct 03, 2019
  233ff982
- AMDGPU/GlobalISel: Allow VGPR to index SGPR register · 56271fe1
  Matt Arsenault authored Oct 03, 2019
  56271fe1
- AMDGPU/GlobalISel: Add some more tests for G_INSERT legalization · 92561839
  Matt Arsenault authored Oct 03, 2019
  92561839
- AMDGPU/GlobalISel: Fix mutationIsSane assert v8s8 and · 3d23e58d
  Matt Arsenault authored Oct 03, 2019
  3d23e58d
- [ModuloSchedule] removeBranch() *before* creating the trip count condition · 9972c992
  James Molloy authored Oct 03, 2019
  9972c992
- [BPF] Handle offset reloc endpoint ending in the middle of chain properly · 02ac7509
  Yonghong Song authored Oct 03, 2019
  02ac7509
- [MSP430] add tests for unwanted shift codegen; NFC (PR43542) · 38c265fe
  Sanjay Patel authored Oct 03, 2019
  38c265fe
- [mips] Use llvm-readobj `-A` flag in test cases. NFC · afe7197f
  Simon Atanasyan authored Oct 03, 2019
  afe7197f
- [AArch64] Static (de)allocation of SVE stack objects. · 4f99b6f0
  Sander de Smalen authored Oct 03, 2019
  4f99b6f0
- [X86] Add test case for v8i64->v8i8 truncate with avx512 and... · 3a6950d3
  Craig Topper authored Oct 03, 2019
  3a6950d3
- AMDGPU/GlobalISel: Expand G_BITCAST legality · 1c135a39
  Matt Arsenault authored Oct 03, 2019
  1c135a39
- [X86] Add DAG combine to turn (bitcast (vbroadcast_load)) into just a... · eb420aa3
  Craig Topper authored Oct 03, 2019
  eb420aa3
- [X86] Add broadcast load folding patterns to NoVLX... · f849f414
  Craig Topper authored Oct 03, 2019
  f849f414
- [AMDGPU] Fix illegal agpr use by VALU · 1384c3a5
  Stanislav Mekhanoshin authored Oct 02, 2019
  1384c3a5
- [X86] Add test cases for suboptimal vselect+setcc splitting. · f5bda7fe
  Craig Topper authored Oct 02, 2019
  f5bda7fe
Oct 02, 2019
- [PowerPC] Fix SH field overflow issue · c7be0679
  Yi-Hong Lyu authored Oct 02, 2019
  c7be0679
- [X86] Rewrite to the vXi1 subvector insertion code to not rely on the value of... · 74c7d6be
  Craig Topper authored Oct 02, 2019
  74c7d6be
- [WebAssembly] Error when using wasm64 for ISel · 5b74c39d
  Thomas Lively authored Oct 02, 2019
  5b74c39d
- [AMDGPU] Extend buffer intrinsics with swizzling · 265e94e6
  Piotr Sobczak authored Oct 02, 2019
  265e94e6
- Reapply r373431 "Switch lowering: omit range check for bit tests when default... · 9330005a
  Hans Wennborg authored Oct 02, 2019
  9330005a
- [AArch64][SVE] Implement int_aarch64_sve_cnt intrinsic · 822b2989
  Kerry McLaughlin authored Oct 02, 2019
  822b2989
- [ModuloSchedule] Peel out prologs and epilogs, generate actual code · 9026518e
  James Molloy authored Oct 02, 2019
  9026518e