Commits · fd2161b710805dd84f1a4874660e5aefc84812a2 · Roger Ferrer / llvm-epi · GitLab

Aug 05, 2014
- [AVX512] Add masking variant and intrinsics for valignd/q · fd2161b7
  Adam Nemet authored Aug 05, 2014
  fd2161b7
- [X86] Increase X86_MAX_OPERANDS from 5 to 6 · 4688a2e5
  Adam Nemet authored Aug 05, 2014
  4688a2e5
- [X86] Add lowering to VALIGN · 164b07fb
  Adam Nemet authored Aug 05, 2014
  164b07fb
- [X86] Separate DAG node for valign and palignr · 2f10cc69
  Adam Nemet authored Aug 05, 2014
  2f10cc69
- [AVX512] alignr: Use suffix rather than name argument to multiclass · d00a05e3
  Adam Nemet authored Aug 05, 2014
  d00a05e3
- [AVX512] Pull everything alignr-related into the multiclass · f92139dd
  Adam Nemet authored Aug 05, 2014
  f92139dd
- Wrap long lines · 1c752d8f
  Adam Nemet authored Aug 05, 2014
  1c752d8f
- Fix return sequence on armv4 thumb · f5fad376
  Jon Roelofs authored Aug 05, 2014
  f5fad376
- Partially revert r214761 that asserted that all concrete debug info variables... · b706b58e
  David Blaikie authored Aug 05, 2014
  b706b58e
- Add accessors for the PPC 403 bank registers. · c4ce4298
  Joerg Sonnenberger authored Aug 05, 2014
  c4ce4298
- Specify that the thumb setend and blx <immed> instructions are not valid on an m-class target · 10457175
  Keith Walker authored Aug 05, 2014
  10457175
- Define stc2/stc2l/ldc2/ldc2l as thumb2 instructions · 292aa3d5
  Keith Walker authored Aug 05, 2014
  292aa3d5
- Accessors for SSR2 and SSR3 on PPC 403. · 936a4c8c
  Joerg Sonnenberger authored Aug 05, 2014
  936a4c8c
- R600/SI: Update MUBUF assembly string to match AMD proprietary compiler · 229d5e66
  Tom Stellard authored Aug 05, 2014
  229d5e66
- R600/SI: Avoid generating REGISTER_LOAD instructions. · b37f7976
  Tom Stellard authored Aug 05, 2014
  b37f7976
- Add dci/ici instructions for PPC 476 and friends. · 41247127
  Joerg Sonnenberger authored Aug 05, 2014
  41247127
- Add mftblo and mftbhi for PPC 4xx. · 048284e1
  Joerg Sonnenberger authored Aug 05, 2014
  048284e1
- Add lswi / stswi for assembler use with a warning to not add patterns · 9dedceb7
  Joerg Sonnenberger authored Aug 05, 2014
  9dedceb7
- AArch64: Add support for instruction prefetch intrinsic · e56de695
  Yi Kong authored Aug 05, 2014
  e56de695
- Teach the SLP Vectorizer that keeping some values live over a callsite can have a cost. · 2b8933c3
  James Molloy authored Aug 05, 2014
  2b8933c3
- [x86] Reformat some code I moved around in a prior commit but left · 183771bd
  Chandler Carruth authored Aug 05, 2014
  183771bd
- Allow binary and for tblgen math. · 6b41a990
  Joerg Sonnenberger authored Aug 05, 2014
  6b41a990
- [x86] Fix a crash and wrong-code bug in the new vector lowering all · 947cef19
  Chandler Carruth authored Aug 05, 2014
  947cef19
- [FastIsel][AArch64] Fix previous commit r214844 (Don't perform... · 95033277
  Juergen Ributzka authored Aug 05, 2014
  95033277
- [FastISel][AArch64] Implement the FastLowerArguments hook. · a126d1ef
  Juergen Ributzka authored Aug 05, 2014
  a126d1ef
- Revert "r214832 - MachineCombiner Pass for selecting faster instruction" · ec100526
  Kevin Qin authored Aug 05, 2014
  ec100526
- [FastISel][AArch64] Don't perform sign-/zero-extension for function arguments... · 51f5326e
  Juergen Ributzka authored Aug 05, 2014
  51f5326e
- Provide convenient access to the zext/sext attributes of function arguments. NFC. · 384c3b5c
  Juergen Ributzka authored Aug 05, 2014
  384c3b5c
- Have MachineFunction cache a pointer to the subtarget to make lookups · fc6de428
  Eric Christopher authored Aug 05, 2014
  fc6de428
- MachineCombiner Pass for selecting faster instruction · 4dbf44b9
  Gerolf Hoflehner authored Aug 05, 2014
  4dbf44b9
- Add TCR register access · 755ffa9b
  Joerg Sonnenberger authored Aug 04, 2014
  755ffa9b
- Add PPC 603's tlbld and tlbli instructions. · 5995e002
  Joerg Sonnenberger authored Aug 04, 2014
  5995e002
- Allow CP10/CP11 operations on ARMv5/v6 · bc0b0378
  Renato Golin authored Aug 04, 2014
  bc0b0378
- [PPC64LE] Fix wrong IR for vec_sld and vec_vsldoi · f04e998e
  Bill Schmidt authored Aug 04, 2014
  f04e998e
- Enable Darwin vararg parameters support in assembler macros. · e3c13468
  Kevin Enderby authored Aug 04, 2014
  e3c13468
- Changed the liveness tracking in the RegisterScavenger · ec7cbd7d
  Pedro Artigas authored Aug 04, 2014
  ec7cbd7d
- Add simplified aliases for access to DCCR, ICCR, DEAR and ESR · 51cf7334
  Joerg Sonnenberger authored Aug 04, 2014
  51cf7334
Aug 04, 2014
- [FastISel][AArch64] Fix shift lowering for i8 and i16 value types. · 53533e88
  Juergen Ributzka authored Aug 04, 2014
  53533e88
- [SDAG] Fix a really, really terrible bug in the DAG combiner. · 40dbd382
  Chandler Carruth authored Aug 04, 2014
  40dbd382
- tlbre / tlbwe / tlbsx / tlbsx. variants for the PPC 4xx CPUs. · 6c3e3852
  Joerg Sonnenberger authored Aug 04, 2014
  6c3e3852