Commits · fee89e43adf3c5fb60e48a0cb22f236323b9b432 · Roger Ferrer / llvm-epi · GitLab

Nov 20, 2014
- Update Makefile following directory removal in r222466 · fee89e43
  Mehdi Amini authored Nov 20, 2014
  fee89e43
- [Hexagon] [NFC] Merging InstPrinter directory in to MCTargetDesc since they... · ff06261a
  Colin LeMahieu authored Nov 20, 2014
  ff06261a
- X86: use the correct alloca symbol for Windows Itanium · 2f3b3f31
  Saleem Abdulrasool authored Nov 20, 2014
  2f3b3f31
- [ELF] Prevent ARM ELF object writer from generating deprecated relocation code R_ARM_PLT32 · 5b9f3522
  Jyoti Allur authored Nov 20, 2014
  5b9f3522
- Fix a typo in a comment. · e9891afa
  Craig Topper authored Nov 20, 2014
  e9891afa
- [Hexagon] Adding A2_xor instruction with IR selection pattern and test. · ac006436
  Colin LeMahieu authored Nov 19, 2014
  ac006436
Nov 19, 2014
- [Hexagon] Adding A2_or instruction with IR selection pattern and test. · 21866546
  Colin LeMahieu authored Nov 19, 2014
  21866546
- [X86] Improved lowering of v4x32 build_vector dag nodes. · 1b657bfc
  Andrea Di Biagio authored Nov 19, 2014
  1b657bfc
- R600/SI: Make SIInstrInfo::isOperandLegal() more strict · e0ddfd11
  Tom Stellard authored Nov 19, 2014
  e0ddfd11
- [mips][micromips] Implement SWM32 and LWM32 instructions · a4c4b5fc
  Zoran Jovanovic authored Nov 19, 2014
  a4c4b5fc
- [mips][microMIPS] Fix opcodes of MFHC1 and MTHC1 instructions. · ffeed441
  Jozef Kolek authored Nov 19, 2014
  ffeed441
- [mips][microMIPS] Implement CodeGen support for 16-bit instruction ADDIUR2. · 4d55b4d7
  Jozef Kolek authored Nov 19, 2014
  4d55b4d7
- [mips][microMIPS] Implement CodeGen support for ADDIUS5 instruction. · 73f64eac
  Jozef Kolek authored Nov 19, 2014
  73f64eac
- [mips][microMIPS] Implement LWXS instruction. · 5f95dd2b
  Jozef Kolek authored Nov 19, 2014
  5f95dd2b
- [mips][microMIPS] Implement SDBBP and RDHWR instructions. · dc62fc4a
  Jozef Kolek authored Nov 19, 2014
  dc62fc4a
- [X86][SSE] pslldq/psrldq byte shifts/rotation for SSE2 · 3ac3b251
  Simon Pilgrim authored Nov 19, 2014
  3ac3b251
- Update SetVector to rely on the underlying set's insert to return a pair<iterator, bool> · 70573dcd
  David Blaikie authored Nov 19, 2014
  70573dcd
- [AArch64] Disable useAA for Cortex-A57. · 2aa06a98
  Hao Liu authored Nov 19, 2014
  2aa06a98
- [AArch64] Enable SeparateConstOffsetFromGEP, EarlyCSE and LICM passes on AArch64 backend. · fd46bea4
  Hao Liu authored Nov 19, 2014
  fd46bea4
- Remove StringMap::GetOrCreateValue in favor of StringMap::insert · 5106ce78
  David Blaikie authored Nov 19, 2014
  5106ce78
- [Aarch64] Customer lowering of CTPOP to SIMD should check for NEON availability · 7a2d1567
  Weiming Zhao authored Nov 19, 2014
  7a2d1567
- R600/SI: Implement areMemAccessesTriviallyDisjoint · c09cc3c5
  Matt Arsenault authored Nov 19, 2014
  c09cc3c5
- R600/SI: Set hasSideEffects = 0 on load and store instructions. · 9a072c19
  Matt Arsenault authored Nov 18, 2014
  9a072c19
- [X86][AVX] 256-bit vector stack unaligned load/stores identification · 9c1e4123
  Simon Pilgrim authored Nov 18, 2014
  9c1e4123
Nov 18, 2014
- [Hexagon] Adding A2_and instruction. · 44fd1c8b
  Colin LeMahieu authored Nov 18, 2014
  44fd1c8b
- [FastISel][AArch64] Also allow folding of sign-/zero-extend and arithmetic · c2508818
  Chad Rosier authored Nov 18, 2014
  c2508818
- [FastISel][AArch64] Also allow folding of sign-/zero-extend and logical · e16d16ae
  Chad Rosier authored Nov 18, 2014
  e16d16ae
- [Hexagon] Adding A2_sub instruction · 38765e6d
  Colin LeMahieu authored Nov 18, 2014
  38765e6d
- [FastISel][AArch64] Follow-up fix for "Fix shift-immediate emission for "zero" shifts." · cdda9308
  Juergen Ributzka authored Nov 18, 2014
  cdda9308
- R600/SI: Move SIFixSGPRCopies to inst selector passes · 162c1010
  Matt Arsenault authored Nov 18, 2014
  162c1010
- [AArch64] Don't optimize all compare instructions. · 7a7c4684
  Juergen Ributzka authored Nov 18, 2014
  7a7c4684
- R600/SI: Make sure resource descriptors are always stored in SGPRs · f0a2107c
  Tom Stellard authored Nov 18, 2014
  f0a2107c
- [Hexagon] Converting from ADD_rr to A2_add which has encoding bits. · efa74e02
  Colin LeMahieu authored Nov 18, 2014
  efa74e02
- [FastISel][AArch64] Fix shift-immediate emission for "zero" shifts. · 4328fd94
  Juergen Ributzka authored Nov 18, 2014
  4328fd94
- Test commit to verify that commit access works. · 52e84e99
  Jozef Kolek authored Nov 18, 2014
  52e84e99
Nov 17, 2014
- Revert "ADT: correctly report isMSVCEnvironment for windows itanium" · d970702a
  Reid Kleckner authored Nov 17, 2014
  d970702a
- ADT: correctly report isMSVCEnvironment for windows itanium · 76f2c770
  Saleem Abdulrasool authored Nov 17, 2014
  76f2c770
- R600/SI: Don't copy flags when extracting subreg · 7480a0e1
  Matt Arsenault authored Nov 17, 2014
  7480a0e1
- R600/SI: Assume SIFixSGPRCopies makes changes · 6f679785
  Matt Arsenault authored Nov 17, 2014
  6f679785
- [X86] Use ADD/SUB instead of INC/DEC for Haswell and Broadwell CPUs · 7de210bd
  Alexey Volkov authored Nov 17, 2014
  7de210bd