Commits · 11ef356d9e3a957fdee16b004c7b8c530ca68a9a · Raul Torres / llvm-target-spread · GitLab

Feb 05, 2021
- [TargetLowering] Use Align in allowsMisalignedMemoryAccesses. · 11ef356d
  Craig Topper authored Feb 04, 2021
  11ef356d
- [WebAssembly] Support single-floating-point immediate value · 698c6b0a
  Dan Gohman authored Feb 04, 2021
  698c6b0a
Feb 04, 2021
- [ARM] Do not emit ldrexd/strexd on Cortex-M chips · aecdf15c
  Ayke van Laethem authored Feb 02, 2021
  aecdf15c
- [AMDGPU] Add f16 to i1 CodeGen patterns. · 50578cf3
  Wen-Heng (Jack) Chung authored Feb 03, 2021
  50578cf3
- [AMDGPU][GlobalISel] Fix v2s16 right shifts · d84e5fda
  Jay Foad authored Feb 04, 2021
  d84e5fda
- [AMDGPU][GlobalISel] Use scalar min/max instructions · b3bb5c3e
  Jay Foad authored Feb 04, 2021
  b3bb5c3e
- [X86] Use VT::changeVectorElementType helper where possible. NFCI. · 31b85e1c
  Simon Pilgrim authored Feb 04, 2021
  
  31b85e1c
- AMDGPU: Add support for amdgpu-unsafe-fp-atomics attribute · 6054a456
  Konstantin Zhuravlyov authored Feb 04, 2021
  6054a456
- [AVR] Remove an assertion that causes generic CodeGen tests to fail · 83e2710e
  Dylan McKay authored Feb 05, 2021
  83e2710e
- [X86] Remove stale TODO comment. NFC. · fa2cdb81
  Simon Pilgrim authored Feb 04, 2021
  fa2cdb81
- [ARM] Handle f16 in GeneratePerfectShuffle · 649a3d00
  David Green authored Feb 04, 2021
  649a3d00
- [AMDGPU] Save all lanes for reserved VGPRs · 6c59dc47
  Sebastian Neubauer authored Feb 04, 2021
  6c59dc47
- [AArch64][GlobalISel] Change store value type from p0 -> s64 to import patterns · 56fcd4ea
  Jessica Paquette authored Feb 02, 2021
  56fcd4ea
- [AArch64][GlobalISel] Emit G_ASSERT_ZEXT in assignValueToAddress for ZExt params · a1f6bb20
  Jessica Paquette authored Jan 29, 2021
  a1f6bb20
Feb 03, 2021
- [Hexagon] Add LLVM instruction definitions for Hexagon V68 · 0bb19851
  Krzysztof Parzyszek authored Feb 03, 2021
  
  0bb19851
- Revert "AMDGPU: Don't consider global pressure when bundling soft clauses" · 477e3fe4
  Matt Arsenault authored Feb 03, 2021
  477e3fe4
- [AMDGPU] Fix multiclass template parameter types. NFC. · 26ec7853
  Jay Foad authored Feb 03, 2021
  26ec7853
- AMDGPU: Move handling of allocation of fixed ABI inputs · 9719f170
  Matt Arsenault authored Jan 09, 2021
  9719f170
- [X86][SSE] Support variable-index float/double vector insertion on SSE41+ targets (PR47924) · 32b7c2fa
  Simon Pilgrim authored Feb 03, 2021
  32b7c2fa
- Revert "[AMDGPU] Add a new Clamp Pattern to the GlobalISel Path." · d49efdc9
  Sebastian Neubauer authored Feb 03, 2021
  d49efdc9
- [AArch64][SVE]Add cost model for broadcast shuffle · 2cbcf3e2
  Caroline Concatto authored Jan 28, 2021
  2cbcf3e2
- [X86] Correct types in tablegen multiclasses found by D95874. · fae6d129
  Wang, Pengfei authored Feb 03, 2021
  fae6d129
- [RISCV] Load/store vector mask types. · 63baeec6
  Hsiangkai Wang authored Dec 16, 2020
  63baeec6
- [RISCV] Add new vector instructions in v0.10. · c7189ba7
  Hsiangkai Wang authored Feb 01, 2021
  c7189ba7
- [PowerPC] [NFC] fix wording typos · b0869a7d
  Chen Zheng authored Feb 02, 2021
  b0869a7d
- AMDGPU: Fix adding extra operands for i128 asm constraints · af2cbe8e
  Matt Arsenault authored Feb 02, 2021
  af2cbe8e
- AMDGPU: Don't consider global pressure when bundling soft clauses · 1e377a27
  Matt Arsenault authored Jan 30, 2021
  1e377a27
Feb 02, 2021
- [AArch64] Homogeneous Prolog and Epilog Size Optimization · 4f58b1bd
  Kyungwoo Lee authored Feb 01, 2021
  4f58b1bd
- [RISCV] Fix incorrect RVV sdiv/udiv lowering · b4106f9c
  Fraser Cormack authored Feb 02, 2021
  b4106f9c
- [RISCV] Correct types in tablegen multiclasses found by D95874. · c4fd1981
  Craig Topper authored Feb 02, 2021
  
  c4fd1981
- [RISCV] Use a ComplexPattern to merge isel patterns for vector load/store with... · 912306ef
  Craig Topper authored Feb 02, 2021
  912306ef
- [ARM] Correct some tablegen operand types. NFC · 3e780616
  David Green authored Feb 02, 2021
  
  3e780616
- [ARM] Mark MVE_VMOV_to_lane_32 as isInsertSubregLike · 2753722b
  David Green authored Feb 02, 2021
  2753722b
- [AMDGPU] Remove unused tmp register · 8b898b19
  Sebastian Neubauer authored Feb 02, 2021
  8b898b19
- [AMDGPU] Save fp/bp after csr saves · 6b6ae583
  Sebastian Neubauer authored Feb 01, 2021
  6b6ae583
- [PowerPC] Materialize 34 bit constants with pli on Power 10. · 288f762b
  Stefan Pintilie authored Feb 02, 2021
  288f762b
- [ARM] Add MVE insert-of-extract pattern · 3a5adf84
  David Green authored Feb 02, 2021
  3a5adf84
- [ARM] Select VINS from vector inserts · c7225756
  David Green authored Feb 02, 2021
  c7225756
- [X86][SSE] LowerINSERT_VECTOR_ELT - pull out repeated EltSizeInBits calls. NFCI. · 8c2e075c
  Simon Pilgrim authored Feb 02, 2021
  
  8c2e075c
- [AMDGPU][MC] Corrected parsing of optional modifiers · 586df384
  Dmitry Preobrazhensky authored Feb 02, 2021
  586df384