Commits · 150ca5143be586e81befc7ab689e1c058ab31710 · Raul Torres / llvm-target-spread · GitLab

Sep 21, 2018
- bpf: check illegal usage of XADD insn return value · 150ca514
  Yonghong Song authored Sep 20, 2018
  150ca514
- [WebAssembly] Add V128 value type to binary format · 6f21a136
  Thomas Lively authored Sep 20, 2018
  6f21a136
Sep 20, 2018
- [SelectionDAG] replace duplicated peekThroughBitcast helper functions; NFCI · 8a1227cc
  Sanjay Patel authored Sep 20, 2018
  8a1227cc
- [X86][SSE] Remove UNPCKL(SHUFFLE)->UNPCKH custom combine · 3e2de767
  Simon Pilgrim authored Sep 20, 2018
  3e2de767
- [X86][SSE] Remove PSHUFLW/PSHUFHW combineRedundantHalfShuffle combine · 46c1dcb1
  Simon Pilgrim authored Sep 20, 2018
  46c1dcb1
- [RISCV][MC] Modify evaluateConstantImm interface to allow reuse from addExpr · 96ed75d0
  Alex Bradbury authored Sep 20, 2018
  96ed75d0
- [RISCV][MC] Improve parsing of jal/j operands · 226f3ef5
  Alex Bradbury authored Sep 20, 2018
  226f3ef5
- Fix for bug 34002 - label generated before it block is finalized. Differential... · ec1efe4e
  Maya Madhavan authored Sep 20, 2018
  ec1efe4e
- [PowerPC] Fix the assert of combineBVOfConsecutiveLoads when element num is 1 · cae9425a
  QingShan Zhang authored Sep 20, 2018
  cae9425a
- [WebAssembly] Renumber SIMD ops · f45de47c
  Thomas Lively authored Sep 20, 2018
  f45de47c
Sep 19, 2018
- AArch64: Add FuseCryptoEOR fusion rules · 28d6a4ac
  Matthias Braun authored Sep 19, 2018
  28d6a4ac
- [ARM] Adjust the feature set for Exynos · 8a6973d6
  Evandro Menezes authored Sep 19, 2018
  8a6973d6
- [ARM] Refactor Exynos feature set (NFC) · c62ab611
  Evandro Menezes authored Sep 19, 2018
  c62ab611
- [X86] Handle COPYs of physregs better (regalloc hints) · 2d0f20cc
  Simon Pilgrim authored Sep 19, 2018
  2d0f20cc
- [x86] change names of vector splitting helper functions; NFC · 1a1c0ee5
  Sanjay Patel authored Sep 19, 2018
  1a1c0ee5
- [mips][microMIPS] Extending size reduction pass with MOVEP · a9e8765e
  Simon Atanasyan authored Sep 19, 2018
  a9e8765e
- [mips][microMIPS] Fix the definition of MOVEP instruction · 852dd83b
  Simon Atanasyan authored Sep 19, 2018
  852dd83b
- [X86] Add initial SimplifyDemandedVectorEltsForTargetNode support · 8191d63c
  Simon Pilgrim authored Sep 19, 2018
  8191d63c
- [AMDGPU] Add instruction selection for i1 to f16 conversion · 6b8d7542
  Carl Ritson authored Sep 19, 2018
  6b8d7542
- [bpf] Symbol sizes and types in object file · 5b476c5a
  Yonghong Song authored Sep 19, 2018
  5b476c5a
- [TableGen][SubtargetEmitter] Add the ability for processor models to describe... · 8b6c314b
  Andrea Di Biagio authored Sep 19, 2018
  8b6c314b
- [DAGCombiner][x86] add transform/hook to decompose integer multiply into shift/add · 4fd2e2a4
  Sanjay Patel authored Sep 19, 2018
  4fd2e2a4
- [AtomicExpandPass]: Add a hook for custom cmpxchg expansion in IR · 79518b02
  Alex Bradbury authored Sep 19, 2018
  79518b02
- [ARM] Fix unwind information for floating point registers · 0b835be7
  Oliver Stannard authored Sep 19, 2018
  0b835be7
- Verify commit access in fixing typo · 7413a438
  Calixte Denizet authored Sep 19, 2018
  7413a438
- [RISCV] Codegen for i8, i16, and i32 atomicrmw with RV32A · 21aea51e
  Alex Bradbury authored Sep 19, 2018
  21aea51e
- [COFF] Emit @feat.00 on 64-bit and set the CFG bit when emitting guardcf tables · 4195eb10
  Hans Wennborg authored Sep 19, 2018
  4195eb10
- [WebAssembly][NFC] Remove extra space in WebAssemblyInstrSIMD.td · ad7e9e9f
  Thomas Lively authored Sep 19, 2018
  ad7e9e9f
- AArch64MacroFusion: Factor out some opcode handling code; NFC · 934be5fe
  Matthias Braun authored Sep 19, 2018
  934be5fe
- ScheduleDAG: Cleanup dumping code; NFC · 726e12cf
  Matthias Braun authored Sep 19, 2018
  726e12cf
Sep 18, 2018
- [WebAssembly] v4f32.abs and v2f64.abs · aaf4e2cb
  Thomas Lively authored Sep 18, 2018
  aaf4e2cb
- [AMDGPU] Match udot8 pattern · f5a28483
  Farhana Aleen authored Sep 18, 2018
  f5a28483
- [RISCV][MC] Use a custom ParserMethod for the bare_symbol operand type · 68f73c12
  Alex Bradbury authored Sep 18, 2018
  68f73c12
- [RISCV][MC] Reject bare symbols for the simm12 operand type · 7d0e18d0
  Alex Bradbury authored Sep 18, 2018
  7d0e18d0
- [RISCV][MC] Tighten up checking of sybol operands to lui and auipc · 74340f18
  Alex Bradbury authored Sep 18, 2018
  74340f18
- [PowerPC] Do not emit record-form rotates when record-form andi/andis suffices · 87c31a61
  Nemanja Ivanovic authored Sep 18, 2018
  87c31a61
- [PowerPC] Optimize compares fed by ANDISo · 6a39d32e
  Nemanja Ivanovic authored Sep 18, 2018
  6a39d32e
- [X86][SSE] LowerShift - pull out repeated getTargetVShiftUniformOpcode calls. NFCI. · e9bf71e7
  Simon Pilgrim authored Sep 18, 2018
  e9bf71e7
- [AArch64] Attempt to parse more operands as expressions · 85d6a559
  David Green authored Sep 18, 2018
  85d6a559
- AMDGPU: Don't form fmed3 if it will require materialization · ebf46143
  Matt Arsenault authored Sep 18, 2018
  ebf46143