Commits · 1fb90133681255d38eed5c75c0fb64c9b090a7f5 · Raul Torres / llvm-target-spread · GitLab

Jun 28, 2018
- AMDGPU: Error on calls from graphics shaders · 1fb90133
  Matt Arsenault authored Jun 28, 2018
  1fb90133
- AMDGPU: Fix AMDGPUCodeGenPrepare using uninitialized AMDGPUAS struct · 12269dda
  Matt Arsenault authored Jun 28, 2018
  12269dda
- AMDGPU: Fix assert on aggregate type kernel arguments · 513e0c0e
  Matt Arsenault authored Jun 28, 2018
  513e0c0e
- Unify sorted asserts to use the existing atomic pattern · f9613b29
  Benjamin Kramer authored Jun 28, 2018
  f9613b29
- [X86] Use PatFrag with hardcoded numbers for FROUND_NO_EXC/FROUND_CURRENT... · ec5d568a
  Craig Topper authored Jun 28, 2018
  ec5d568a
- [X86] Change how we prefer shift by immediate over folding a load into a shift. · ab70f588
  Craig Topper authored Jun 28, 2018
  ab70f588
Jun 27, 2018
- [X86] Make folding table checking threadsafe · e214f046
  Benjamin Kramer authored Jun 27, 2018
  e214f046
- [X86] In X86DAGToDAGISel::PreprocessISelDAG, make sure we don't access N after we delete it. · 880e34ed
  Craig Topper authored Jun 27, 2018
  880e34ed
- [RISCV] Add machine function pass to merge base + offset · 9b65ffb0
  Sameer AbuAsal authored Jun 27, 2018
  9b65ffb0
- [X86] Fix unmatched parenthesis in r335768 · b0d57a53
  Fangrui Song authored Jun 27, 2018
  b0d57a53
- [X86] Teach the disassembler to use %eiz/%riz instead of NoRegister when the... · 6bea2c7f
  Craig Topper authored Jun 27, 2018
  6bea2c7f
- [globalisel][legalizer] Add AtomicOrdering to LegalityQuery and use it in AArch64 · bdeb880d
  Daniel Sanders authored Jun 27, 2018
  bdeb880d
- [MachineOutliner] Don't outline sequences where x16/x17/nzcv are live across · f472f615
  Jessica Paquette authored Jun 27, 2018
  f472f615
- [X86] Use bts/btr/btc for single bit set/clear/complement of a variable bit position · 812fcb35
  Craig Topper authored Jun 27, 2018
  812fcb35
- [X86] Rename the autoupgraded of packed fp compare and fpclass intrinsics that... · 31cbe75b
  Craig Topper authored Jun 27, 2018
  31cbe75b
- [AMDGPU] Convert rcp to rcp_iflag · 1a1687f1
  Stanislav Mekhanoshin authored Jun 27, 2018
  1a1687f1
- [AArch64] Reverting FP16 vcvth_n_s64_f16 to fix · 31632715
  Luke Geeson authored Jun 27, 2018
  31632715
- [AArch64] Add custom lowering for v4i8 trunc store · cadcfed7
  Adhemerval Zanella authored Jun 27, 2018
  cadcfed7
- [NEON] Support vldNq intrinsics in AArch32 (LLVM part) · 7231598f
  Ivan A. Kosarev authored Jun 27, 2018
  7231598f
- [AArch64] Remove Duplicate FP16 Patterns with same encoding, match on existing patterns · 68cb233c
  Luke Geeson authored Jun 27, 2018
  68cb233c
- AMDGPU/NFC: Fix typo in comment · 30f03b3b
  Konstantin Zhuravlyov authored Jun 27, 2018
  30f03b3b
- [X86] Don't store register and memory FMA3 opcodes in the same X86InstrFMA3Group. · 33aba0eb
  Craig Topper authored Jun 27, 2018
  33aba0eb
Jun 26, 2018
- AMDGPU: Silence unused warnings in waitcnt insertion pass in release build · 77747770
  Konstantin Zhuravlyov authored Jun 26, 2018
  77747770
- [X86][AsmParser] Recommit r335658 · 67599c2e
  Jessica Paquette authored Jun 26, 2018
  67599c2e
- Revert "[X86][AsmParser] Emit an error when RIP-relative instructions are used in 32-bit mode" · 0a80af07
  Jessica Paquette authored Jun 26, 2018
  0a80af07
- [X86][AsmParser] Emit an error when RIP-relative instructions are used in 32-bit mode · 0e40d4bf
  Jessica Paquette authored Jun 26, 2018
  0e40d4bf
- [AMDGPU] Add llvm.amdgcn.fmad.ftz intrinsic · dacda79e
  Stanislav Mekhanoshin authored Jun 26, 2018
  dacda79e
- AMDGPU: Add pass to lower kernel arguments to loads · 8c4a3523
  Matt Arsenault authored Jun 26, 2018
  8c4a3523
- [Hexagon] Add a "generic" cpu · b7169c43
  Brendon Cahoon authored Jun 26, 2018
  b7169c43
- [TargetLowering] isVectorClearMaskLegal - use ArrayRef<int> instead of const SmallVectorImpl<int>& · aa2bf2be
  Simon Pilgrim authored Jun 26, 2018
  aa2bf2be
- [X86,ARM] Retain split-stack prolog check for sibling calls · 3190993a
  Than McIntosh authored Jun 26, 2018
  3190993a
- ARM: correctly decode VFP instructions following unpredictable t2IT · b73efb85
  Tim Northover authored Jun 26, 2018
  b73efb85
- ARM: diagnose unpredictable IT instructions · bf548581
  Tim Northover authored Jun 26, 2018
  bf548581
- [X86] Just use ArrayRef instead of SmallVectorImpl in a few static method arguments. NFCI. · bfaa0922
  Simon Pilgrim authored Jun 26, 2018
  bfaa0922
- [X86] Don't use getScalarShiftAmountTy to get the immediate type for target... · 08dae168
  Craig Topper authored Jun 26, 2018
  08dae168
- [WebAssembly] Fix lowering of varargs functions with non-legal fixed arguments. · 910ba33d
  Dan Gohman authored Jun 26, 2018
  910ba33d
- [X86] Use XOR for SUB (C, X) during isel if will help fold an immediate · c42ed4e3
  Craig Topper authored Jun 26, 2018
  c42ed4e3
- [WebAssembly] Fix a typo in a comment. · fd2f7aeb
  Dan Gohman authored Jun 26, 2018
  fd2f7aeb
- [X86] Redefine avx512 packed fpclass intrinsics to return a vXi1 mask and... · 689e363f
  Craig Topper authored Jun 26, 2018
  689e363f
- Revert r335562 and 335563 "[X86] Redefine avx512 packed fpclass intrinsics to... · 6f4fdfa9
  Craig Topper authored Jun 26, 2018
  6f4fdfa9