Commits · 292f7257118a6e270f93acb14dc6119588e9e427 · Raul Torres / llvm-target-spread · GitLab

Feb 05, 2020
- [AArch64][GlobalISel] Fold G_ASHR into TB(N)Z bit calculation · 292f7257
  Jessica Paquette authored Feb 03, 2020
  292f7257
- Reapply: [SVE] Fix bug in simplification of scalable vector instructions · b03f3fbd
  Christopher Tetreault authored Feb 03, 2020
  b03f3fbd
- AMDGPU/GlobalISel: Prefer merge/unmerge ops to legalize TFE · 7bffa972
  Matt Arsenault authored Jan 26, 2020
  7bffa972
- [AArch64][GlobalISel] Fix one use check in getTestBitReg · a82a28ae
  Jessica Paquette authored Feb 04, 2020
  a82a28ae
- AMDGPU/GlobalISel: Legalize TFE image result loads · e65e6d05
  Matt Arsenault authored Jan 17, 2020
  e65e6d05
- [PGO][PGSO] Tune flags for profile guided size optimization. · b70f23f5
  Hiroshi Yamauchi authored Jan 17, 2020
  b70f23f5
- AMDGPU: Fix divergence analysis of control flow intrinsics · 096cd991
  Matt Arsenault authored Jan 31, 2020
  096cd991
- NFC: fix unused var warnings in no-assert builds · 9f507bfd
  Jordan Rupprecht authored Feb 05, 2020
  
  9f507bfd
- Resubmit^2: [JumpThreading] Thread jumps through two basic blocks · 4698bf14
  Kazu Hirata authored Feb 05, 2020
  4698bf14
- [IRCE] Make IRCE a Function pass. · 67904db2
  Alina Sbirlea authored Jan 27, 2020
  67904db2
- AMDGPU/GlobalISel: Legalize llvm.amdgcn.s.buffer.load · 69cc9f30
  Matt Arsenault authored Jan 30, 2020
  69cc9f30
- [WPD/LowerTypeTests] Delay lowering/removal of type tests until after ICP · 748bb5a0
  Teresa Johnson authored Jan 22, 2020
  748bb5a0
- AMDGPU/GlobalISel: Fix processing new phi in waterfall loop · 307e0d54
  Matt Arsenault authored Feb 01, 2020
  307e0d54
- AMDGPU/GlobalISel: Don't use legal v2s16 G_BUILD_VECTOR · dfa9420f
  Matt Arsenault authored Jan 04, 2020
  dfa9420f
- [ARM][TargetParser] Improve handling of dependencies between target features · 3627c91e
  Momchil Velikov authored Feb 05, 2020
  3627c91e
- [ARM][MVE] LowOverheadLoops: DCE on the iteration count setup expression · 01022af5
  Sjoerd Meijer authored Feb 05, 2020
  01022af5
- [ARM] Correct syntax of the CLRM insn · a328536c
  Momchil Velikov authored Feb 05, 2020
  a328536c
- [MCA] Remove verification check on MayLoad and MayStore. NFCI · aaaeac61
  Andrea Di Biagio authored Feb 05, 2020
  aaaeac61
- visitINSERT_VECTOR_ELT - pull out repeated dyn_cast. NFCI. · 4592bb71
  Simon Pilgrim authored Feb 05, 2020
  4592bb71
- [ARM][LowOverheadLoops] Fix loop count chain · 56427528
  Sam Parker authored Feb 05, 2020
  56427528
- [ARM][LowOverheadLoops] Ensure memory predication · 4c7f8192
  Sam Parker authored Feb 05, 2020
  4c7f8192
- [X86] Fix missing load latencies (PR36894) · 8616bd41
  Simon Pilgrim authored Feb 05, 2020
  8616bd41
- [AMDGPU] Fix lowering a16 image intrinsics · 163e33b2
  Sebastian Neubauer authored Jan 23, 2020
  163e33b2
- [AMDGPU] Use v3f32 type in image instructions · 3bc7ffda
  Sebastian Neubauer authored Jan 29, 2020
  3bc7ffda
- [yaml2obj][obj2yaml] - Simplify format of the SHT_LLVM_ADDRSIG section. · 60f161eb
  Georgii Rymar authored Feb 03, 2020
  60f161eb
- [DebugInfo] Avoid the call site param for mem instrs with multiple defs · de90d73e
  Djordje Todorovic authored Feb 05, 2020
  de90d73e
- [X86] Add a DAG combine for (i32 (sext (i8 (x86isd::setcc_carry)))) -> (i32... · a3d489e8
  Craig Topper authored Feb 03, 2020
  a3d489e8
- AMDGPU/EG,CM: Implement fsqrt using recip(rsqrt(x)) instead of x * rsqrt(x) · e6686adf
  Jan Vesely authored Feb 04, 2020
  e6686adf
- Revert "[WebAssembly][InstrEmitter] Foundation for multivalue call lowering" · 649aba93
  Thomas Lively authored Feb 03, 2020
  649aba93
- AMDGPU: Correct memory size for image intrinsics · 9260d01f
  Matt Arsenault authored Jan 28, 2020
  9260d01f
- DebugInfo: Hash DW_OP_convert in loclists when using Split DWARF · ec50e10d
  David Blaikie authored Feb 04, 2020
  ec50e10d
- DebugInfo: Add a couple of missing COFF sections to make convert-loclist.ll pass on Windows · def55a8e
  David Blaikie authored Feb 04, 2020
  
  def55a8e
- Revert "[WebAssembly] Split and recombine multivalue calls for ISel" · 8acedb59
  Thomas Lively authored Feb 03, 2020
  8acedb59
- [BPF] disable ReduceLoadWidth during SelectionDag phase · d96c1bba
  Yonghong Song authored Feb 04, 2020
  d96c1bba
- [WebAssembly] Enable recently implemented SIMD operations · 27748363
  Thomas Lively authored Jan 30, 2020
  27748363
- [Remarks] Fix gcc build · 31258878
  Francis Visoiu Mistrih authored Feb 04, 2020
  
  31258878
- [Remarks] Extend the RemarkStreamer to support other emitters · 7531a503
  Francis Visoiu Mistrih authored Oct 28, 2019
  7531a503
- [NFCI] Update according to style. · 1c03cc5a
  Alina Sbirlea authored Feb 04, 2020
  1c03cc5a
- Fix some more -Wrange-loop-analysis warnings in AArch64TargetParser · f3bacd07
  Reid Kleckner authored Feb 04, 2020
  
  f3bacd07
- [X86] Add custom lowering for lrint/llrint to either cvtss2si/cvtsd2si or fist. · 016f42e3
  Craig Topper authored Feb 04, 2020
  016f42e3