Commits · 2ca6c422d2d025821390260232307567191a7deb · Raul Torres / llvm-target-spread · GitLab

Jul 28, 2020
- [FunctionAttrs] Rename functionattrs -> function-attrs · 2ca6c422
  Arthur Eubanks authored Jul 28, 2020
  2ca6c422
- GlobalISel: Translate llvm.convert.{to|from}.fp16 intrinsics · 97b5fb78
  Matt Arsenault authored Jul 25, 2020
  97b5fb78
- AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat · a4edc046
  Matt Arsenault authored Jul 12, 2020
  a4edc046
- [SCEV] Add additional tests. · be2ea29e
  Florian Hahn authored Jul 12, 2020
  be2ea29e
- [AArch64][SVE] Fix epilogue for SVE when the stack is realigned. · cda2eb3a
  Sander de Smalen authored Jul 28, 2020
  cda2eb3a
- [AArch64][SVE] Don't align the last SVE callee save. · 26b4ef36
  Sander de Smalen authored Jul 27, 2020
  26b4ef36
- [AArch64][SVE] Don't support fixedStack for SVE objects. · 54492a58
  Sander de Smalen authored Jul 27, 2020
  54492a58
- [DWARFYAML] Add support for emitting custom range list content. · 22ec861d
  Xing GUO authored Jul 28, 2020
  22ec861d
- Re-land "[PowerPC] Remove QPX/A2Q BGQ/BGP CNK support" · d28f8672
  Jinsong Ji authored Jul 28, 2020
  d28f8672
- [yaml2obj] - Add a way to override sh_type section field. · bd93f5ce
  Georgii Rymar authored Jul 28, 2020
  bd93f5ce
- ARM: make Thumb1 instructions non-flag-setting in IT block. · 39108f4c
  Tim Northover authored Jul 27, 2020
  39108f4c
- [PowerPC] Split s34imm into two types · 97470897
  Stefan Pintilie authored Jul 27, 2020
  97470897
- [llvm-readobj] - Add comments and formatting to mips-options-sec.test and mips-reginfo.test. NFCI. · 93b79155
  Georgii Rymar authored Jul 28, 2020
  93b79155
- [llvm-readelf] Symbol index in symbol table printing is not reset · 67070d98
  Mikhail Kalashnikov authored Jul 28, 2020
  67070d98
- [Attributor] Track AA dependency using dependency graph · 5ee07dc5
  Luofan Chen authored Jul 28, 2020
  5ee07dc5
- [X86][SSE] Attempt to match OP(SHUFFLE(X,Y),SHUFFLE(X,Y)) -> SHUFFLE(HOP(X,Y)) · 18211177
  Simon Pilgrim authored Jul 28, 2020
  18211177
- [llvm-readelf] - Do not treat SHT_ANDROID_RELR sections the same as SHT_RELR. · ee068aaf
  Georgii Rymar authored Jul 23, 2020
  ee068aaf
- [PowerPC] test case for adding dq form to isLegalAddressingMode, nfc · c2abdec7
  Chen Zheng authored Jul 28, 2020
  
  c2abdec7
- [GVN] Rewrite IsValueFullyAvailableInBlock(): no recursion, less false-negatives · e40315d2
  Roman Lebedev authored Jul 28, 2020
  e40315d2
- [X86] Detect if EFLAGs is live across XBEGIN pseudo instruction. Add it as... · 647e861e
  Craig Topper authored Jul 27, 2020
  647e861e
- [X86] Add support for {disp32} to control size of jmp and jcc instructions in the assembler · 25f193fb
  Craig Topper authored Jul 27, 2020
  25f193fb
- [X86] Properly encode a 32-bit address with an index register and no base register in 16-bit mode. · a0ebac52
  Craig Topper authored Jul 27, 2020
  a0ebac52
- Supplement instr profile with sample profile. · a23f6234
  Wei Mi authored Jul 08, 2020
  a23f6234
- [llvm-readelf] Fix emitting incorrect number of spaces in '--hex-dump'. · 6bf989b9
  Xing GUO authored Jul 28, 2020
  6bf989b9
- GlobalISel: Don't fail translate on intrinsics with metadata · 5f802be4
  Matt Arsenault authored Jul 21, 2020
  
  5f802be4
- TableGen/GlobalISel: Allow output instructions with multiple defs · ee3feef5
  Matt Arsenault authored Jul 13, 2020
  ee3feef5
- [llvm][CodeGen] Addressing modes for SVE ldN. · adb28e0f
  Francesco Petrogalli authored Jul 06, 2020
  adb28e0f
Jul 27, 2020
- Revert "[PowerPC] Remove QPX/A2Q BGQ/BGP CNK support" · bf544fa1
  Jinsong Ji authored Jul 27, 2020
  bf544fa1
- Rename t2-reduce-size -> thumb2-reduce-size · beb7e3bb
  Arthur Eubanks authored Jul 27, 2020
  beb7e3bb
- [PowerPC] Remove QPX/A2Q BGQ/BGP CNK support · adffce71
  Jinsong Ji authored Jul 27, 2020
  adffce71
- [Attributor][NFC] Add tests to noalias.ll · bef19abc
  Shinji Okumura authored Jul 28, 2020
  bef19abc
- Prefix some AArch64/ARM passes with "aarch64-"/"arm-" · 2a672767
  Arthur Eubanks authored Jul 27, 2020
  2a672767
- [X86][SSE] Relax 128-bit restriction on... · 4d84d949
  Simon Pilgrim authored Jul 27, 2020
  4d84d949
- Reland [llvm-exegesis] Add benchmark latency option on X86 that uses LBR for... · ee7caa75
  Vy Nguyen authored Jul 27, 2020
  ee7caa75
- [TableGen][CGS] Print better errors on overlapping InstRW · 88ce9f9b
  Jon Roelofs authored Jul 22, 2020
  88ce9f9b
- [XCOFF][AIX] Handle llvm.used and llvm.compiler.used global array · c25f61cf
  jasonliu authored Jul 27, 2020
  c25f61cf
- [AArch64] fjcvtzs,rmif,cfinv,setf* all clobber nzcv · f5e1ec8c
  Jon Roelofs authored Jul 14, 2020
  f5e1ec8c
- Revert "Re-apply:" Emit DW_OP_implicit_value for Floating point constants"" · 7c182663
  Amy Kwan authored Jul 27, 2020
  7c182663
- [X86][AVX] Fold extract_subvector(truncate(x),0) -> truncate(extract_subvector(x),0) · ab4ffa52
  Simon Pilgrim authored Jul 27, 2020
  ab4ffa52
- [JumpThreading] ProcessBranchOnXOR(): bailout if any pred ends in indirect branch (PR46857) · 1da98345
  Roman Lebedev authored Jul 27, 2020
  1da98345