Commits · 2db0ea03ba60111bcf417f1a12e8781425ec276a · Raul Torres / llvm-target-spread · GitLab

Nov 05, 2010
- Hook up the '.code {16|32}' directive to the streamer. · 2db0ea03
  Jim Grosbach authored Nov 05, 2010
  2db0ea03
- Hook up the '.thumb_func' directive to the streamer. · c6db8ce5
  Jim Grosbach authored Nov 05, 2010
  c6db8ce5
- Fix past-o. · 0fe92e3f
  Jim Grosbach authored Nov 05, 2010
  0fe92e3f
- MC'ize the '.code 16' and '.thumb_func' ARM directives. · 5a2c68d3
  Jim Grosbach authored Nov 05, 2010
  5a2c68d3
- Disallow the certain NEON modified-immediate forms when generating vorr or vbic. · a4076924
  Owen Anderson authored Nov 05, 2010
  a4076924
- MC'ize simple ARMConstantValue entry emission (with a FIXME). · ff9e507d
  Jim Grosbach authored Nov 05, 2010
  ff9e507d
- Add codegen and encoding support for the immediate form of vbic. · 30c4892e
  Owen Anderson authored Nov 05, 2010
  30c4892e
- Enable MachO writing for ARM/Darwin. Lots of stuff still doesn't work · 2bab7570
  Jim Grosbach authored Nov 05, 2010
  2bab7570
- Allow targets to specify the MachO CPUType/CPUSubtype information. · 46c2acbc
  Jim Grosbach authored Nov 05, 2010
  46c2acbc
- Add FIXME. · 1df82e67
  Jim Grosbach authored Nov 05, 2010
  1df82e67
Nov 04, 2010
- When passing a huge parameter using the byval mechanism, a long · 98512315
  Duncan Sands authored Nov 04, 2010
  98512315
- In the calling convention logic, ValVT is always a legal type, · 71049f78
  Duncan Sands authored Nov 04, 2010
  71049f78
- Fix @llvm.prefetch isel. Selecting between pld / pldw using the first... · 21acf9fb
  Evan Cheng authored Nov 04, 2010
  21acf9fb
- Add ARM fixup info for load/store label references. Probably will need a bit of · 0fb841fd
  Jim Grosbach authored Nov 04, 2010
  0fb841fd
- Add encoding for VSTR. · c002463a
  Bill Wendling authored Nov 04, 2010
  c002463a
- Teach ARM Target to use the tblgen support for generating an MC'ized · 2eed7a13
  Jim Grosbach authored Nov 03, 2010
  2eed7a13
- Covert VORRIMM to be produced via early target-specific DAG combining, rather than legalization. · bc9b31c4
  Owen Anderson authored Nov 03, 2010
  bc9b31c4
Nov 03, 2010
- Add support for code generation of the one register with immediate form of vorr. · 07473070
  Owen Anderson authored Nov 03, 2010
  07473070
- trailing whitespace · 49b0c45e
  Jim Grosbach authored Nov 03, 2010
  49b0c45e
- Optimize generated code for integer materialization a bit. · e4dd7378
  Eric Christopher authored Nov 03, 2010
  e4dd7378
- Unlike a lot of NEON instructions, vext isn't _actually_ parameterized by element size. Instead, · bb81f80a
  Owen Anderson authored Nov 03, 2010
  bb81f80a
- Add codegen patterns for VST1-lane instructions. Radar 8599955. · 7d0ac84a
  Bob Wilson authored Nov 03, 2010
  7d0ac84a
- Check for extractelement with a variable operand for the element number. · ceb49296
  Bob Wilson authored Nov 03, 2010
  ceb49296
- Simplify uses of MVT and EVT. An MVT can be compared directly · 14627770
  Duncan Sands authored Nov 03, 2010
  14627770
- Inside the calling convention logic LocVT is always a simple · f5dda01f
  Duncan Sands authored Nov 03, 2010
  f5dda01f
- Fix preload instruction isel. Only v7 supports pli, and only v7 with mp... · 8740ee36
  Evan Cheng authored Nov 03, 2010
  8740ee36
- Add support to match @llvm.prefetch to pld / pldw / pli. rdar://8601536 . · 6f360425
  Evan Cheng authored Nov 03, 2010
  6f360425
- Put the PC encoding in the correct bit position. · 6552a109
  Bill Wendling authored Nov 03, 2010
  6552a109
- Invert these branches by default, it makes assembly comparisons a little · c63d846a
  Eric Christopher authored Nov 03, 2010
  c63d846a
- The MC code couldn't handle ARM LDR instructions with negative offsets: · e84eb99c
  Bill Wendling authored Nov 03, 2010
  e84eb99c
- Remove unused function. · fd967014
  Jim Grosbach authored Nov 03, 2010
  fd967014
- Remove the no longer used 'Modifier' optional operand to the ARM · e7f7de95
  Jim Grosbach authored Nov 03, 2010
  e7f7de95
- Remove unused function. · 50ba3c09
  Jim Grosbach authored Nov 03, 2010
  50ba3c09
- Break ARM addrmode4 (load/store multiple base address) into its constituent · c6af2b40
  Jim Grosbach authored Nov 03, 2010
  c6af2b40
- Two sets of changes. Sorry they are intermingled. · debf9c50
  Evan Cheng authored Nov 03, 2010
  debf9c50
- Modify scheduling itineraries to correct instruction latencies (not operand · 634ab6c2
  Evan Cheng authored Nov 03, 2010
  634ab6c2
- Make sure we're only storing a single bit here. · 1e43892e
  Eric Christopher authored Nov 02, 2010
  1e43892e
- per a suggestion by Frits van Bommel, mark all MBlaze Pseudo · 9c9bfb68
  Chris Lattner authored Nov 02, 2010
  9c9bfb68
- Revert r118097 to fix buildbots. · 0ebd1fd5
  Owen Anderson authored Nov 02, 2010
  0ebd1fd5
- Completely reject instructions that have an operand in their · cc5dce89
  Chris Lattner authored Nov 02, 2010
  cc5dce89