Commits · 32e78c3ff7172bacc6759518c3167014938c3dda · Raul Torres / llvm-target-spread · GitLab

May 03, 2016
- [X86][SSSE3] Missing combine opportunity to simplify to a MOVQ shuffle · 32e78c3f
  Simon Pilgrim authored May 03, 2016
  32e78c3f
- [AVX512] Add support for commutative MAX/MIN . In general VMAX{PS,PD} and... · 58c07806
  Igor Breger authored May 03, 2016
  58c07806
- [AVX512] Fix lowerV4X128VectorShuffle to select correctly input operands . · ab076c68
  Igor Breger authored May 03, 2016
  ab076c68
- Fix uppercase typo · bb85aef7
  Matthias Braun authored May 03, 2016
  bb85aef7
- AArch64/optimizeCondBranch: Remove earlier kill flag when forming TBZ · e25bbd0b
  Matthias Braun authored May 03, 2016
  e25bbd0b
- [MachineBlockPlacement] Let the target optimize the branches at the end. · 776e6de5
  Quentin Colombet authored May 02, 2016
  776e6de5
- [X86] Model FAULTING_LOAD_OP as a terminator and branch. · 4e1d389a
  Quentin Colombet authored May 02, 2016
  4e1d389a
May 02, 2016
- AMDGPU: Custom lower v2i32 loads and stores · bcdfee70
  Matt Arsenault authored May 02, 2016
  bcdfee70
- AMDGPU/SI: Use v_readfirstlane_b32 when restoring SGPRs spilled to scratch · 154c9cdd
  Tom Stellard authored May 02, 2016
  154c9cdd
- AMDGPU: Make i64 loads/stores promote to v2i32 · 2b957b5a
  Matt Arsenault authored May 02, 2016
  2b957b5a
- [X86][AVX2] Added 128-bit wide shuffle test · 21b2c566
  Simon Pilgrim authored May 02, 2016
  21b2c566
- ARM: fix handling of SUB immediates in peephole opt. · c08db184
  Tim Northover authored May 02, 2016
  c08db184
- [NVPTX] Fix sign/zero-extending ldg/ldu instruction selection · 9a6ea2c2
  Justin Holewinski authored May 02, 2016
  9a6ea2c2
- AMDGPU/SI: Use the hazard recognizer to break SMEM soft clauses · 1f520e5c
  Tom Stellard authored May 02, 2016
  1f520e5c
- [WebAssembly] Rename memory_size intrinsic to current_memory · 31680dd8
  Derek Schuff authored May 02, 2016
  31680dd8
- AMDGPU/SI: Use hazard recognizer to detect DPP hazards · a27007eb
  Tom Stellard authored May 02, 2016
  a27007eb
- Enable the X86 call frame optimization for the 64-bit targets that allow it. · 0fe4632b
  David L Kreitzer authored May 02, 2016
  0fe4632b
- [SystemZ] Temporarily disable codegen test int-add-12.ll. · 1eb3486a
  Jonas Paulsson authored May 02, 2016
  1eb3486a
May 01, 2016
- [AVX512] VPACKUSWB/VPACKSSWB should not be encoded with EVEX.W=1. While there... · b6da6540
  Craig Topper authored May 01, 2016
  b6da6540
- getelementptr instruction, support index vector of EVT. · 110af565
  Igor Breger authored May 01, 2016
  110af565
- Change AVX512 braodcastsd/ss patterns interaction with spilling . New... · 131008fb
  Igor Breger authored May 01, 2016
  131008fb
- [AVX512] Prefer AVX512 VPACK instructions over AVX/AVX2 instructions when VLX... · e430de8b
  Craig Topper authored May 01, 2016
  e430de8b
Apr 30, 2016
- AMDGPU/SI: Remove wait state handling for SMRD in SIInsertWaits · c51e4468
  Tom Stellard authored Apr 30, 2016
  c51e4468
- AMDGPU/SI: Enable the post-ra scheduler · cb6ba62d
  Tom Stellard authored Apr 30, 2016
  cb6ba62d
- [MBP] Use Function::optForSize() instead of checking OptimizeForSize directly. · 4afe0425
  Haicheng Wu authored Apr 29, 2016
  4afe0425
Apr 29, 2016
- AMDGPU: Fix crash with unreachable terminators. · 701c21ea
  Matt Arsenault authored Apr 29, 2016
  701c21ea
- Differential Revision: http://reviews.llvm.org/D19733 · 7da9b445
  Sriraman Tallam authored Apr 29, 2016
  7da9b445
- AMDGPU: Add kernarg.segment.ptr intrinsic · dc4ebad6
  Matt Arsenault authored Apr 29, 2016
  dc4ebad6
- DAGCombiner: Reduce truncated shl width · ab2232cf
  Matt Arsenault authored Apr 29, 2016
  ab2232cf
- [PPC] Enable shuffling of VSX vectors · fa3e0429
  Guozhi Wei authored Apr 29, 2016
  fa3e0429
- [mips][FastISel] A store is not a load. · d8bceb9d
  Simon Dardis authored Apr 29, 2016
  d8bceb9d
- [Hexagon] Optimize addressing modes for load/store · f5cbac93
  Krzysztof Parzyszek authored Apr 29, 2016
  f5cbac93
- AMDGPU/SI: Add offset field to ds_permute/ds_bpermute instructions · 92b24f32
  Tom Stellard authored Apr 29, 2016
  92b24f32
- AMDGPU/SI: Assembler: Unify parsing/printing of operands. · 4f672a34
  Nikolay Haustov authored Apr 29, 2016
  4f672a34
- RegisterPressure: Fix default lanemask for missing regunit intervals · f3619b82
  Matthias Braun authored Apr 29, 2016
  f3619b82
Apr 28, 2016
- [PowerPC] Fix the EH_SjLj_Setup pseudo. · 7b329578
  Marcin Koscielnicki authored Apr 28, 2016
  7b329578
- [RDF] Improve handling of inline-asm · c5a4e264
  Krzysztof Parzyszek authored Apr 28, 2016
  c5a4e264
- AMDGPU: Emit error if too much LDS is used · 1c4d0efe
  Matt Arsenault authored Apr 28, 2016
  1c4d0efe
- Reset the TopRPTracker's position in ScheduleDAGMILive::initQueues · 7ea9a529
  Krzysztof Parzyszek authored Apr 28, 2016
  7ea9a529
- AMDGPU: Fix mishandling array allocations when promoting alloca · c5fce690
  Matt Arsenault authored Apr 28, 2016
  c5fce690