Commits · 4082a6c2ec2c27414c65852bc175036f440f10f5 · Raul Torres / llvm-target-spread · GitLab

Dec 02, 2014
- Remove unused function. · cdfa931d
  Asiri Rathnayake authored Dec 02, 2014
  cdfa931d
- Add support for ARM modified-immediate assembly syntax. · a0199b9a
  Asiri Rathnayake authored Dec 02, 2014
  a0199b9a
- Emit Tag_ABI_FP_denormal correctly in fast-math mode. · 15f91c52
  Charlie Turner authored Dec 02, 2014
  15f91c52
- Fix variable used only in assertion. · ceb44dfd
  Nick Lewycky authored Dec 02, 2014
  ceb44dfd
- Try to fix a bot failure due to a variable used only in an assert. · 8e302cdb
  Philip Reames authored Dec 01, 2014
  8e302cdb
Dec 01, 2014
- [Statepoints 2/4] Statepoint infrastructure for garbage collection: MI & x86-64 Backend · 0365f1a3
  Philip Reames authored Dec 01, 2014
  0365f1a3
- [NVPTX] Do not emit .weak symbols for NVPTX · 5b62eb9b
  Jingyue Wu authored Dec 01, 2014
  5b62eb9b
- [AArch64] Don't combine "select (setcc i1 LHS, RHS), vL, vR". · d0ce058f
  Ahmed Bougacha authored Dec 01, 2014
  d0ce058f
- [AArch64] Fix v2i8->i16 bitcast legalization. · 87946320
  Ahmed Bougacha authored Dec 01, 2014
  87946320
- ARM: lower tail calls correctly when using GHC calling convention. · 3024b553
  Tim Northover authored Dec 01, 2014
  3024b553
- R600/SI: Various instruction format bit test cleanups · c5f174d0
  Matt Arsenault authored Dec 01, 2014
  c5f174d0
- The andi16, addiusp and jraddiusp micromips instructions were missing... · b682ddf3
  Vladimir Medic authored Dec 01, 2014
  b682ddf3
- [PowerPC] Fix unwind info with dynamic stack realignment · 1f0a44e6
  Jay Foad authored Dec 01, 2014
  1f0a44e6
- Add post-decode checking of HVC instruction. · 30895f9a
  Charlie Turner authored Dec 01, 2014
  30895f9a
- Add Thumb HVC and ERET virtualisation extension instructions. · 7de905cd
  Charlie Turner authored Dec 01, 2014
  7de905cd
- Add ARM ERET and HVC virtualisation extension instructions. · 4d88ae20
  Charlie Turner authored Dec 01, 2014
  4d88ae20
- Fix capitalization. NFC. · 107d13c2
  Akira Hatanaka authored Dec 01, 2014
  107d13c2
Nov 30, 2014
- [PowerPC] Add asm support for cache-inhibited ld/st instructions · 378107da
  Hal Finkel authored Nov 30, 2014
  378107da
Nov 29, 2014
- Target triple OS detection tidyup. NFC · 2bfd9129
  Simon Pilgrim authored Nov 29, 2014
  2bfd9129
- [mips][microMIPS] Implement NOP aliases · c7e220f6
  Jozef Kolek authored Nov 29, 2014
  c7e220f6
Nov 28, 2014
- R600/SI: Fix assertion on sign extend of 3 vectors · 8596f719
  Matt Arsenault authored Nov 28, 2014
  8596f719
- Revert "Masked Vector Load and Store Intrinsics." · 9bc81fbe
  Duncan P. N. Exon Smith authored Nov 28, 2014
  9bc81fbe
- Enable FeatureFastUAMem for btver2 · e57f3c0a
  Sanjay Patel authored Nov 28, 2014
  e57f3c0a
- Fix wrong encoding of MRSBanked. · db6c5e7a
  Charlie Turner authored Nov 28, 2014
  db6c5e7a
- Add missing 'override' keyword. · 44586dc4
  Craig Topper authored Nov 28, 2014
  44586dc4
Nov 27, 2014
- Stop using ArrayRef of a const type. · a38e5cbf
  Tim Northover authored Nov 27, 2014
  a38e5cbf
- AArch64: treat [N x Ty] as a block during procedure calls. · 3c55ccac
  Tim Northover authored Nov 27, 2014
  3c55ccac
- [mips][microMIPS] Implement SWM16 and LWM16 instructions · f9a02500
  Zoran Jovanovic authored Nov 27, 2014
  f9a02500
- [mips][microMIPS] Implement BREAK16 and SDBBP16 instructions · 56a6a7d3
  Jozef Kolek authored Nov 27, 2014
  56a6a7d3
- [mips] Add synci instruction. · b4484d62
  Daniel Sanders authored Nov 27, 2014
  b4484d62
- [mips][microMIPS] Implement disassembler support for 16-bit instructions LI16,... · aa2b9278
  Jozef Kolek authored Nov 27, 2014
  aa2b9278
- Stop uppercasing build attribute data. · 8d433691
  Charlie Turner authored Nov 27, 2014
  8d433691
Nov 26, 2014
- R600/SI: Use ZeroOrNegativeOneBooleanContent · fcdddf96
  Matt Arsenault authored Nov 26, 2014
  fcdddf96
- [Hexagon] Adding cmp* immediate form instructions. · 6e0f9f8d
  Colin LeMahieu authored Nov 26, 2014
  6e0f9f8d
- [mips][microMIPS] Implement disassembler support for 16-bit instructions... · 315e7eca
  Jozef Kolek authored Nov 26, 2014
  315e7eca
- [Hexagon] Adding and64, or64, and xor64 instructions. · 31abe337
  Colin LeMahieu authored Nov 26, 2014
  31abe337
- R600/SI: Create e64 versions of and/or/xor in SILowerI1Copies · b9350895
  Matt Arsenault authored Nov 26, 2014
  b9350895
- Update AArch64 ELF relocations to ABI 1.0 · 40f08faa
  Will Newton authored Nov 26, 2014
  40f08faa
- AVX-512: Scalar ERI intrinsics · 905a5a60
  Elena Demikhovsky authored Nov 26, 2014
  905a5a60
- Replace neverHasSideEffects=1 with hasSideEffects=0 in all .td files. · c50d64b0
  Craig Topper authored Nov 26, 2014
  c50d64b0