Commits · 411773d2276f88cae075cf75f0aadb0310368fbf · Raul Torres / llvm-target-spread · GitLab

Nov 15, 2018
- [RISCV] Mark C.EBREAK instruction as having side effects · f809d899
  Alex Bradbury authored Nov 15, 2018
  f809d899
- [RISCV] Mark FREM as Expand · 77272404
  Alex Bradbury authored Nov 15, 2018
  77272404
- [RISCV] Introduce the RISCVMatInt::generateInstSeq helper · 22c091fc
  Alex Bradbury authored Nov 15, 2018
  22c091fc
Nov 12, 2018
- [RISCV] Support .option relax and .option norelax · 9c03e4ca
  Alex Bradbury authored Nov 12, 2018
  9c03e4ca
Nov 09, 2018
- [RISCV] Avoid unnecessary XOR for seteq/setne 0 · 1cc2d0b9
  Alex Bradbury authored Nov 09, 2018
  1cc2d0b9
Nov 02, 2018
- [RISCV] Add some missing expansions for floating-point intrinsics · 52c27785
  Alex Bradbury authored Nov 02, 2018
  52c27785
Oct 25, 2018
- [RISCV] Use PatFrags for variable shift patterns · 74d4931d
  Alex Bradbury authored Oct 25, 2018
  74d4931d
Oct 13, 2018
- [RISCV] Eliminate unnecessary masking of promoted shift amounts · 748d080e
  Alex Bradbury authored Oct 12, 2018
  748d080e
Oct 12, 2018
- [RISCV] Fix disassembling of fence instruction with invalid field · 0a5fcefa
  Ana Pazos authored Oct 11, 2018
  0a5fcefa
Oct 06, 2018
- [RISCV] Compress addiw rd, x0, simm6 to c.li rd, simm6 · 639df9e4
  Alex Bradbury authored Oct 06, 2018
  639df9e4
Oct 04, 2018
- [RISCV] Support named operands for CSR instructions. · 9d6c5532
  Ana Pazos authored Oct 04, 2018
  9d6c5532
- [RISCV] Remove overzealous is64Bit checks · 5bf3b20e
  Alex Bradbury authored Oct 04, 2018
  5bf3b20e
- [RISCV] Bugfix for floats passed on the stack with the ILP32 ABI on RV32F · e96b7c88
  Alex Bradbury authored Oct 04, 2018
  e96b7c88
- [RISCV][NFC] Fix naming of RISCVISelLowering::{LowerRETURNADDR,LowerFRAMEADDR} · 0e16766b
  Alex Bradbury authored Oct 04, 2018
  0e16766b
- [RISCV] Handle redundant SplitF64+BuildPairF64 pairs in a DAGCombine · 5ac0a2fc
  Alex Bradbury authored Oct 03, 2018
  5ac0a2fc
- [RISCV][NFC] Refactor LocVT<->ValVT converstion in RISCVISelLowering · 1dbfdeb6
  Alex Bradbury authored Oct 03, 2018
  1dbfdeb6
Oct 03, 2018
- [RISCV][NFCI] Handle redundant splitf64+buildpairf64 pairs during instruction selection · ce904995
  Alex Bradbury authored Oct 03, 2018
  ce904995
- [RISCV][NFC] Refactor RISCVDAGToDAGISel::Select · d33ffe9b
  Alex Bradbury authored Oct 03, 2018
  d33ffe9b
- [RISCV] Gate float<->int and double<->int conversion patterns on IsRV32 · d934032e
  Alex Bradbury authored Oct 03, 2018
  d934032e
- [RISCV] Remove XLenVT==i32 assumptions from RISCVInstrInfo td · d464ed8c
  Alex Bradbury authored Oct 03, 2018
  d464ed8c
- [RISCV] Gate simm32 materialisation pattern and SW pattern on IsRV32 · a9ac5994
  Alex Bradbury authored Oct 03, 2018
  a9ac5994
Sep 20, 2018
- [RISCV][MC] Modify evaluateConstantImm interface to allow reuse from addExpr · 96ed75d0
  Alex Bradbury authored Sep 20, 2018
  96ed75d0
- [RISCV][MC] Improve parsing of jal/j operands · 226f3ef5
  Alex Bradbury authored Sep 20, 2018
  226f3ef5
Sep 19, 2018
- [RISCV] Codegen for i8, i16, and i32 atomicrmw with RV32A · 21aea51e
  Alex Bradbury authored Sep 19, 2018
  21aea51e
Sep 18, 2018
- [RISCV][MC] Use a custom ParserMethod for the bare_symbol operand type · 68f73c12
  Alex Bradbury authored Sep 18, 2018
  68f73c12
- [RISCV][MC] Reject bare symbols for the simm12 operand type · 7d0e18d0
  Alex Bradbury authored Sep 18, 2018
  7d0e18d0
- [RISCV][MC] Tighten up checking of sybol operands to lui and auipc · 74340f18
  Alex Bradbury authored Sep 18, 2018
  74340f18
Sep 13, 2018
- [RISCV][MC] Reject bare symbols for the simm6 and simm6nonzero operand types · 065b0887
  Ana Pazos authored Sep 13, 2018
  065b0887
- [RISCV] Fix decoding of invalid instruction with C extension enabled. · b0799dda
  Ana Pazos authored Sep 13, 2018
  b0799dda
Sep 10, 2018
- [Target] Untangle disassemblers · 27c769d2
  Benjamin Kramer authored Sep 10, 2018
  27c769d2
Sep 07, 2018
- [RISCV] Fix crash in decoding instruction with unknown floating point rounding mode · b2ed11a0
  Ana Pazos authored Sep 07, 2018
  b2ed11a0
- [RISCV] Fix AddressSanitizer heap-buffer-overflow in disassembling · b97d1894
  Ana Pazos authored Sep 07, 2018
  b97d1894
Aug 30, 2018
- [RISCV] Fixed SmallVector.h Assertion `idx < size()' · 6b34051b
  Ana Pazos authored Aug 30, 2018
  6b34051b
Aug 27, 2018
- [RISCV] atomic_store_nn have a different layout to regular store · fe282170
  Roger Ferrer Ibanez authored Aug 27, 2018
  fe282170
Aug 25, 2018
- [RISCV] Fixed Assertion`Kind == Immediate && "Invalid type access!"' failed. · ecc65edd
  Ana Pazos authored Aug 24, 2018
  ecc65edd
- [RISCV] Fix std::advance slowness · 61b28ede
  Ana Pazos authored Aug 24, 2018
  61b28ede
Aug 17, 2018
- [RISCV] Remove unused function · 734a04ea
  Roger Ferrer Ibanez authored Aug 17, 2018
  734a04ea
Aug 14, 2018
- [RISCV] Fix incorrect use of MCInstBuilder · c8f4dbbc
  Roger Ferrer Ibanez authored Aug 14, 2018
  c8f4dbbc
- Test commit: fix punctuation · 5d94b25f
  Chih-Mao Chen authored Aug 14, 2018
  5d94b25f
Aug 09, 2018
- [RISC-V] Fixed alias for addi x2, x2, 0 · 10de2349
  Ana Pazos authored Aug 09, 2018
  10de2349