Commits · 49e033f41d45b8fdb09bfc2b195986704039a765 · Raul Torres / llvm-target-spread · GitLab

Apr 24, 2017
- CodeGen: Add a hook for getFenceOperandTy · fd23a0c0
  Yaxun Liu authored Apr 24, 2017
  fd23a0c0
- X86RegisterInfo: eliminateFrameIndex: Avoid code duplication; NFC · f9796b76
  Matthias Braun authored Apr 24, 2017
  f9796b76
- AMDGPU: Add StackPtr and FramePtr registers to MFI · 1c0ae397
  Matt Arsenault authored Apr 24, 2017
  1c0ae397
- AMDGPU: Move trap lowering to DAG · 3e02538a
  Matt Arsenault authored Apr 24, 2017
  3e02538a
- AMDGPU: Move v_readlane lane select from VGPR to SGPR · 5dea6451
  Nicolai Haehnle authored Apr 24, 2017
  5dea6451
- [GlobalISel][X86] Lower FormalArgument/Ret using G_MERGE_VALUES/G_UNMERGE_VALUES. · 87aafa07
  Igor Breger authored Apr 24, 2017
  87aafa07
- AMDGPU: Fix crash when scheduling non-memory SMRD instructions · ef449787
  Nicolai Haehnle authored Apr 24, 2017
  ef449787
- [SystemZ] Update kill-flag in splitMove(). · 1e864857
  Jonas Paulsson authored Apr 24, 2017
  1e864857
- [ARM] GlobalISel: Legalize s8 and s16 G_(S|U)DIV · f53865da
  Diana Picus authored Apr 24, 2017
  f53865da
- [Arch64AsmParser] better diagnostic for isb · e5b8557d
  Sjoerd Meijer authored Apr 24, 2017
  e5b8557d
- [ARM] GlobalISel: Support G_(S|U)DIV for s32 · b70e88bd
  Diana Picus authored Apr 24, 2017
  b70e88bd
- [ARM] GlobalISel: Select G_CONSTANT with CImm operands · 95a8aa93
  Diana Picus authored Apr 24, 2017
  95a8aa93
Apr 23, 2017
- [X86][SSE] Add scheduler class support for SSE42 (PCMPGT) instructions · 06d62633
  Simon Pilgrim authored Apr 23, 2017
  06d62633
- Revert "[APInt] Fix a few places that use APInt::getRawData to operate within the normal API." · 4abfb3d7
  Renato Golin authored Apr 23, 2017
  4abfb3d7
- [X86][MPX] Add load & store instructions of bnd values to getLoadStoreRegOpcode function. · 137c44fe
  Ayman Musa authored Apr 23, 2017
  137c44fe
- [APInt] Fix a few places that use APInt::getRawData to operate within the normal API. · 474e5de7
  Craig Topper authored Apr 23, 2017
  474e5de7
- [APInt] Use operator<<= where possible. NFC · cdd5ae66
  Craig Topper authored Apr 23, 2017
  cdd5ae66
- [APInt] Use operator<<= instead of shl where possible. NFC · 5f68af08
  Craig Topper authored Apr 23, 2017
  5f68af08
- [APInt] Use ashInPlace where possible. · ae9672c9
  Craig Topper authored Apr 23, 2017
  ae9672c9
Apr 22, 2017
- [globalisel][tablegen] Revise API for ComplexPattern operands to improve flexibility. · 2deea187
  Daniel Sanders authored Apr 22, 2017
  2deea187
- AArch64FrameLowering: Check if the ExtraCSSpill register is actually unused · d78597ec
  Matthias Braun authored Apr 21, 2017
  d78597ec
Apr 21, 2017
- Re-commit r301040 "X86: Don't emit zero-byte functions on Windows" · 9b9a5358
  Hans Wennborg authored Apr 21, 2017
  9b9a5358
- Revert r301040 "X86: Don't emit zero-byte functions on Windows" · 04593000
  Hans Wennborg authored Apr 21, 2017
  04593000
- X86: Don't emit zero-byte functions on Windows · cb3e8107
  Hans Wennborg authored Apr 21, 2017
  cb3e8107
- ARM: make sure we use all entries in a vector before forming a vpaddl. · e31cf3f8
  Tim Northover authored Apr 21, 2017
  e31cf3f8
- AMDGPU/GFX9: Enable FastFMAF32 · f628406b
  Konstantin Zhuravlyov authored Apr 21, 2017
  f628406b
- AMDGPU: Temporarily disable packed inlinable literals (v2f16, v2i16) · 3d1cc88c
  Konstantin Zhuravlyov authored Apr 21, 2017
  3d1cc88c
- AMDGPU: Fix S_PACK_HH_B32_B16 · 88938d4e
  Konstantin Zhuravlyov authored Apr 21, 2017
  88938d4e
- [AMDGPU] Handle SI_MASKED_UNREACHABLE in instruction emitter · 15a96b1d
  Yaxun Liu authored Apr 21, 2017
  15a96b1d
- Revert "X86RegisterInfo: eliminateFrameIndex: Avoid code duplication; NFC" · 1a906240
  Matthias Braun authored Apr 21, 2017
  1a906240
- AMDGPU: Do not lower fast unsafe div for safe, f32, with fp32 denormals · c4b18e70
  Konstantin Zhuravlyov authored Apr 21, 2017
  c4b18e70
- [AArch64] Improve code generation for logical instructions taking · 22e839f4
  Akira Hatanaka authored Apr 21, 2017
  22e839f4
- [AArch64] Refactor instruction selection lowering for addresses. NFCI · a7c4a521
  Joel Jones authored Apr 21, 2017
  a7c4a521
- ARM: don't try to create an i8 -> i32 vpaddl. · 1061ccca
  Tim Northover authored Apr 21, 2017
  1061ccca
- [globalisel][tablegen] Import SelectionDAG's rule predicates and support the equivalent in GIRule. · e7b0d660
  Daniel Sanders authored Apr 21, 2017
  e7b0d660
- [AArch64][Falkor] Refine modeling of store-release exclusive instructions. · 428556c5
  Chad Rosier authored Apr 21, 2017
  428556c5
- [Mips] Document Mips Backend Relocation Principles · 97aaa23a
  Joel Jones authored Apr 21, 2017
  97aaa23a
- [AArch64][Falkor] Refine resource needs of STRQ with register offset. · d631b9e5
  Chad Rosier authored Apr 21, 2017
  d631b9e5
- Revert r300964 + r300970 - [globalisel][tablegen] Import SelectionDAG's rule... · 419efdd5
  Daniel Sanders authored Apr 21, 2017
  419efdd5
- [AArch64][Falkor] Refine loads/stores that require an extra LD pipe. · 537defee
  Chad Rosier authored Apr 21, 2017
  537defee