Commits · 5c62598b0da96ae7df1b4be69ae7f2b0ce63febc · Raul Torres / llvm-target-spread · GitLab

Apr 13, 2018
- [AArch64][SVE] Asm: Support for contiguous ST1 (scalar+imm) store instructions. · 5c62598b
  Sander de Smalen authored Apr 13, 2018
  5c62598b
- [X86] Remove OpndItins/SizeItins from all sse instruction defs (PR37093) · ae0c2711
  Simon Pilgrim authored Apr 13, 2018
  ae0c2711
- [NEON] Support intrinsic for scalar and vector versions of the VRINTN instruction · f533a6e5
  Ivan A. Kosarev authored Apr 13, 2018
  f533a6e5
- [NFC] fix trivial typos in comments · 372ffa15
  Hiroshi Inoue authored Apr 13, 2018
  372ffa15
- [AArch64][SVE] Asm: Add support for parsing and printing SVE vector lists. · ea626e37
  Sander de Smalen authored Apr 13, 2018
  ea626e37
- [X86] Introduce cldemote instruction · 604be442
  Gabor Buella authored Apr 13, 2018
  604be442
- [X86] Remove the pmuldq/pmuldq intrinsics and replace with native IR. · 254ed028
  Craig Topper authored Apr 13, 2018
  254ed028
- [X86] Remove unused MoveLoadStoreItins/ShiftOpndItins schedule class wrappers. · 1f070c33
  Simon Pilgrim authored Apr 12, 2018
  1f070c33
- [X86] Remove x86 InstrItinClass entries (PR37093) · 6551d405
  Simon Pilgrim authored Apr 12, 2018
  6551d405
Apr 12, 2018
- AArch64: Introduce a DAG combine for folding offsets into addresses. · 00db326b
  Peter Collingbourne authored Apr 12, 2018
  00db326b
- [X86] Remove InstrItinClass entries from all x86 instruction defs (PR37093) · 0e45634f
  Simon Pilgrim authored Apr 12, 2018
  0e45634f
- [X86] Remove InstrItinClass entries from SSE/AVX instructions defs (PR37093) · e9376b9f
  Simon Pilgrim authored Apr 12, 2018
  e9376b9f
- [X86] Remove explicit SSE/AVX schedule itineraries from defs (PR37093) · 577ae24f
  Simon Pilgrim authored Apr 12, 2018
  577ae24f
- [RISCV] Add c.mv rs1, rs2 pattern for addi rs1, rs2, 0 · e8b7ff30
  Sameer AbuAsal authored Apr 12, 2018
  e8b7ff30
- [X86] Remove remaining gpr schedule itineraries (PR37093) · 35935c06
  Simon Pilgrim authored Apr 12, 2018
  35935c06
- [X86] Introduce LLVM wbinvd intrinsic · 297c1387
  Gabor Buella authored Apr 12, 2018
  297c1387
- [X86] Remove gpr shift/extension schedule itineraries (PR37093) · dec781c1
  Simon Pilgrim authored Apr 12, 2018
  dec781c1
- [Power9]Legalize and emit code for converting (Un)Signed DWord to Quad-Precision · 10367eb4
  Lei Huang authored Apr 12, 2018
  10367eb4
- [MIPS GlobalISel] remove superfluous #includes (NFC) · 667e2130
  Petar Jovanovic authored Apr 12, 2018
  667e2130
- [AArch64] Move AFI->setRedZone(false) to top of emitPrologue · 8aa6cd5c
  Jessica Paquette authored Apr 12, 2018
  8aa6cd5c
- [mips] Correct the predicates of the load/store (double)word for coprocessor 3. · d886aba3
  Simon Dardis authored Apr 12, 2018
  d886aba3
- [X86] Remove AES/CLMUL/CRC32/LDDQU/MOVNT/POPCNT/SHA schedule itineraries (PR37093) · 8904a86f
  Simon Pilgrim authored Apr 12, 2018
  8904a86f
- [AArch64][AsmParser] Unify 'addVectorListOperands' functions. · 525e3225
  Sander de Smalen authored Apr 12, 2018
  525e3225
- [X86] Remove remaining system/special schedule itineraries (PR37093) · 294556d4
  Simon Pilgrim authored Apr 12, 2018
  294556d4
- [mips] Correct the predicates for special nops, tlb ctrl instrs, software breakpoint and prefx. · a5a3c38c
  Simon Dardis authored Apr 12, 2018
  a5a3c38c
- [X86] Remove system/control schedule itineraries (PR37093) · 0cd0fbd8
  Simon Pilgrim authored Apr 12, 2018
  0cd0fbd8
- [AArch64][AsmParser] Make parse function for VectorLists generic to other vector types. · 650234ba
  Sander de Smalen authored Apr 12, 2018
  650234ba
- [RISCV] Change function alignment to 4 bytes, and 2 bytes for RVC · b48b027d
  Shiva Chen authored Apr 12, 2018
  b48b027d
- [X86] Remove CMOV/SETCC schedule itineraries (PR37093) · 69e0e8e3
  Simon Pilgrim authored Apr 12, 2018
  69e0e8e3
- [X86] Remove MMX/3DNow schedule itineraries (PR37093) · 10e3bdaa
  Simon Pilgrim authored Apr 12, 2018
  10e3bdaa
- [X86] Remove X87 schedule itineraries (PR37093) · 32d36814
  Simon Pilgrim authored Apr 12, 2018
  32d36814
- [SystemZ] Use ResourceCycles=30 for FPd unit (NFC). · 319ce96f
  Jonas Paulsson authored Apr 12, 2018
  319ce96f
- [SystemZ] Remove FullInstRWOverlapCheck from SchedMachineModels. · e3f53e5d
  Jonas Paulsson authored Apr 12, 2018
  e3f53e5d
- [HexagonMachineScheduler] Remove local (copied) getWeakLeft(). · 26e171f0
  Jonas Paulsson authored Apr 12, 2018
  26e171f0
- [MachineScheduler] NFC refactoring · e8f1ac70
  Jonas Paulsson authored Apr 12, 2018
  e8f1ac70
- [RISCV] Codegen support for RV32D floating point comparison operations · 21d28fe8
  Alex Bradbury authored Apr 12, 2018
  21d28fe8
- [RISCV] Codegen support for RV32D floating point conversion operations · 60baa2e0
  Alex Bradbury authored Apr 12, 2018
  60baa2e0
- [RISCV] Add codegen support for RV32D floating point arithmetic operations · 5d0dfa5e
  Alex Bradbury authored Apr 12, 2018
  5d0dfa5e
- [RISCV] Codegen support for RV32D floating point load/store, fadd.d, calling conv · 0b4175f1
  Alex Bradbury authored Apr 12, 2018
  0b4175f1
- Test commit access · bedca0b4
  Yan Luo authored Apr 12, 2018
  bedca0b4