Commits · 67aa18f165640374cf0e0a6226dc793bbda6e74f · Raul Torres / llvm-target-spread · GitLab

Jun 28, 2018
- [AMDGPU] Early expansion of 32 bit udiv/urem · 67aa18f1
  Stanislav Mekhanoshin authored Jun 28, 2018
  67aa18f1
- [AMDGPU] Overload llvm.amdgcn.fmad.ftz to support f16 · 298a6159
  Stanislav Mekhanoshin authored Jun 28, 2018
  298a6159
- [DEBUG_INFO, NVPTX] Add test for .debug_loc section, NFC. · 5f6e51d5
  Alexey Bataev authored Jun 28, 2018
  5f6e51d5
- Add a PhiValuesAnalysis pass to calculate the underlying values of phis · bdbbd838
  John Brawn authored Jun 28, 2018
  bdbbd838
- Revert "Add support for generating a call graph profile from Branch Frequency Info." · 269eb21e
  Benjamin Kramer authored Jun 28, 2018
  269eb21e
- [ARM] Parallel DSP Pass · c89ca558
  Sjoerd Meijer authored Jun 28, 2018
  c89ca558
- AMDGPU: Error on calls from graphics shaders · 1fb90133
  Matt Arsenault authored Jun 28, 2018
  1fb90133
- AMDGPU: Fix assert on aggregate type kernel arguments · 513e0c0e
  Matt Arsenault authored Jun 28, 2018
  513e0c0e
- [DAGCombiner] Ensure we use the correct CC result type in visitSDIV · abebe4c7
  Simon Pilgrim authored Jun 28, 2018
  abebe4c7
- [SCCP] Mark CFG as preserved. · 388af14f
  Florian Hahn authored Jun 28, 2018
  388af14f
- [IndVarSimplify] Ignore unreachable users of truncs · f5ba3718
  Max Kazantsev authored Jun 28, 2018
  f5ba3718
- Add support for generating a call graph profile from Branch Frequency Info. · 5bf1ead3
  Michael J. Spencer authored Jun 27, 2018
  5bf1ead3
Jun 27, 2018
- [RISCV] Add machine function pass to merge base + offset · 9b65ffb0
  Sameer AbuAsal authored Jun 27, 2018
  9b65ffb0
- [InstCombine] add tests for vector-select-of-binops with 2 variables; NFC · 1ef49be8
  Sanjay Patel authored Jun 27, 2018
  1ef49be8
- [WebAssembly] Try fixing test/CodeGen/WebAssembly/vector_sdiv.ll · 5dc371a7
  Fangrui Song authored Jun 27, 2018
  5dc371a7
- [X86] Teach the disassembler to use %eiz/%riz instead of NoRegister when the... · 6bea2c7f
  Craig Topper authored Jun 27, 2018
  6bea2c7f
- [globalisel][legalizer] Add AtomicOrdering to LegalityQuery and use it in AArch64 · bdeb880d
  Daniel Sanders authored Jun 27, 2018
  bdeb880d
- [ThinLTO] Fix test · 6835c284
  Teresa Johnson authored Jun 27, 2018
  6835c284
- [ThinLTO] Modify test to help diagnose bot failures · 6535b356
  Teresa Johnson authored Jun 27, 2018
  6535b356
- [DAGCombiner] restrict (float)((int) f) --> ftrunc with no-signed-zeros · d052de85
  Sanjay Patel authored Jun 27, 2018
  d052de85
- [ThinLTO] Print names in function import debug messages when available · 7e7b13d0
  Teresa Johnson authored Jun 27, 2018
  7e7b13d0
- [MachineOutliner] Don't outline sequences where x16/x17/nzcv are live across · f472f615
  Jessica Paquette authored Jun 27, 2018
  f472f615
- [InstCombine] add more tests for shuffle with different binops; NFC · 7e45aebe
  Sanjay Patel authored Jun 27, 2018
  7e45aebe
- [X86] Use bts/btr/btc for single bit set/clear/complement of a variable bit position · 812fcb35
  Craig Topper authored Jun 27, 2018
  812fcb35
- [X86] Add test cases for D48606. · 069628b4
  Craig Topper authored Jun 27, 2018
  069628b4
- [X86][SSE] Add missing AVX512 rotation tests · 8a02b253
  Simon Pilgrim authored Jun 27, 2018
  8a02b253
- [X86] Rename the autoupgraded of packed fp compare and fpclass intrinsics that... · 31cbe75b
  Craig Topper authored Jun 27, 2018
  31cbe75b
- [AMDGPU] Convert rcp to rcp_iflag · 1a1687f1
  Stanislav Mekhanoshin authored Jun 27, 2018
  1a1687f1
- [AArch64] Reverting FP16 vcvth_n_s64_f16 to fix · 31632715
  Luke Geeson authored Jun 27, 2018
  31632715
- [AArch64] Add custom lowering for v4i8 trunc store · cadcfed7
  Adhemerval Zanella authored Jun 27, 2018
  cadcfed7
- [NEON] Support vldNq intrinsics in AArch32 (LLVM part) · 7231598f
  Ivan A. Kosarev authored Jun 27, 2018
  7231598f
- [DAGCombiner] visitSDIV - add special case handling for (sdiv X, 1) -> X in pow2 expansion · d3e583a5
  Simon Pilgrim authored Jun 27, 2018
  d3e583a5
- [X86][SSE] Include MIN_SIGNED element in non-uniform SDIV pow2 tests · 41afbcb9
  Simon Pilgrim authored Jun 27, 2018
  41afbcb9
- [DAGCombiner] Fold SDIV(%X, MIN_SIGNED) -> SELECT(%X == MIN_SIGNED, 1, 0) · dfbcc66a
  Simon Pilgrim authored Jun 27, 2018
  dfbcc66a
- [DAGCombiner] Don't accept signbit sdiv divisors in sdiv-by-pow2 vector expansion (PR37569) · 0a566bc0
  Simon Pilgrim authored Jun 27, 2018
  0a566bc0
- [AArch64] Remove Duplicate FP16 Patterns with same encoding, match on existing patterns · 68cb233c
  Luke Geeson authored Jun 27, 2018
  68cb233c
- [InstCombine] Avoid creating mis-sized dbg.values in commonCastTransforms() · f6c0b41f
  Vedant Kumar authored Jun 27, 2018
  f6c0b41f
- [Debugify] Handle failure to get fragment size when checking dbg.values · d13536e9
  Vedant Kumar authored Jun 27, 2018
  d13536e9
- [Debugify] Diagnose mis-sized dbg.values · b9c1a234
  Vedant Kumar authored Jun 26, 2018
  b9c1a234
- Revert "[asan] Instrument comdat globals on COFF targets" · 289a7d4c
  Evgeniy Stepanov authored Jun 26, 2018
  289a7d4c