Commits · 746da5fe2a407254753965473728ee574d1b906c · Raul Torres / llvm-target-spread · GitLab

Aug 19, 2015
- Map %fprs to %asr6 in the Sparc assembler parser. · 7d180c59
  Joerg Sonnenberger authored Aug 19, 2015
  7d180c59
- Revert "[X86] Widen the 'AND' mask if doing so shrinks the encoding size" · 85508e80
  Tobias Grosser authored Aug 19, 2015
  85508e80
- [X86] Do not lower scalar sdiv/udiv to a shifts + mul sequence when optimizing for minsize · 9fe42604
  Michael Kuperstein authored Aug 19, 2015
  9fe42604
- [TLI] Refactor "is integer division cheap" queries. · dcdab4cd
  Michael Kuperstein authored Aug 19, 2015
  dcdab4cd
- MIR Serialization: Serialize the operand's bit mask target flags. · f3630113
  Alex Lorenz authored Aug 18, 2015
  f3630113
- use TLI.allowsMemoryAccess() to check if memory accesses are fast; NFCI · 5c55fbc5
  Sanjay Patel authored Aug 18, 2015
  5c55fbc5
Aug 18, 2015
- Load/store instructions for floating points with address space require SparcV9. · b0ce8747
  Joerg Sonnenberger authored Aug 18, 2015
  b0ce8747
- [WinEH] Calculate state numbers for the new EH representation · 0ad363ee
  David Majnemer authored Aug 18, 2015
  0ad363ee
- MachineRegisterInfo: Introduce isPhysRegUsed() · d55bcf26
  Matthias Braun authored Aug 18, 2015
  d55bcf26
- use minSize wrapper; NFCI · 1cd6d88e
  Sanjay Patel authored Aug 18, 2015
  1cd6d88e
- [AArch64] Simplify the logic for computing in bounds offset. NFC. · 3dd0e942
  Chad Rosier authored Aug 18, 2015
  3dd0e942
- [mips] Expand JAL instructions when PIC is enabled. · 63f4a5dc
  Daniel Sanders authored Aug 18, 2015
  63f4a5dc
- [mips][microMIPS] Implement DDIV, DMOD, DDIVU and DMODU instructions · 2fe8466f
  Zoran Jovanovic authored Aug 18, 2015
  2fe8466f
- [mips][microMIPS] Implement SW and SWE instructions · a6593ff6
  Zoran Jovanovic authored Aug 18, 2015
  a6593ff6
- [mips] Make the MipsAsmParser capable of knowing whether PIC mode is enabled or not. · a6994440
  Daniel Sanders authored Aug 18, 2015
  a6994440
- [mips] Correct -Woverflow warning in r245208 without changing signedness of the constant. · f1ae367a
  Daniel Sanders authored Aug 18, 2015
  f1ae367a
- Align SP adjustment in function getSPAdjust · f66d3844
  Guozhi Wei authored Aug 17, 2015
  f66d3844
Aug 17, 2015
- [SPARC]: recognize '.' as the start of an assembler expression. · 685a7d1a
  Douglas Katzman authored Aug 17, 2015
  685a7d1a
- [ARM] Fix crash when targetting CPU without NEON · 974838f2
  James Molloy authored Aug 17, 2015
  974838f2
- [CostModel][AArch64] Increase cost of vector insert element and add missing cast costs · b322aa6f
  Silviu Baranga authored Aug 17, 2015
  b322aa6f
- [CostModel][ARM] Increase cost of insert/extract operations · d5ac2693
  Silviu Baranga authored Aug 17, 2015
  d5ac2693
- Correcting a -Woverflow warning where 0xFFFF was overflowing an implicit constant conversion. · aa3d810b
  Aaron Ballman authored Aug 17, 2015
  aa3d810b
- [mips] [IAS] Add support for the DLA pseudo-instruction and fix problems with DLI · a39ef1c6
  Daniel Sanders authored Aug 17, 2015
  a39ef1c6
- Remove hand-rolled matching for fmin and fmax. · 88edc824
  James Molloy authored Aug 17, 2015
  88edc824
- Rip out hand-rolled matching code for VMIN, VMAX, VMINNM and VMAXNM · c617be55
  James Molloy authored Aug 17, 2015
  c617be55
- [PM] Port ScalarEvolution to the new pass manager. · 2f1fd165
  Chandler Carruth authored Aug 17, 2015
  2f1fd165
Aug 16, 2015
- Add missing include guard. · 178c4652
  Yaron Keren authored Aug 16, 2015
  178c4652
- [X86] Widen the 'AND' mask if doing so shrinks the encoding size · 1a59e49f
  David Majnemer authored Aug 16, 2015
  1a59e49f
Aug 15, 2015
- [x86] enable machine combiner reassociations for scalar single-precision minimums · 40d4eb40
  Sanjay Patel authored Aug 15, 2015
  40d4eb40
- Silence VS2015 warning. · 8b2a031c
  Yaron Keren authored Aug 15, 2015
  8b2a031c
- [DAGCombiner] Attempt to mask vectors before zero extension instead of after. · 0750c846
  Simon Pilgrim authored Aug 15, 2015
  0750c846
- AMDGPU/SI: Only look at live out SGPR defs · 588732bd
  Matt Arsenault authored Aug 15, 2015
  588732bd
- Remove redundant TargetFrameLowering::getFrameIndexOffset virtual · 5567bafe
  James Y Knight authored Aug 15, 2015
  5567bafe
- [WebAssembly] Add Relooper · d4698e1b
  JF Bastien authored Aug 15, 2015
  d4698e1b
- AMDGPU/SI: Fix printing useless info with amdhsa · 297ae311
  Matt Arsenault authored Aug 15, 2015
  297ae311
- AMDGPU/SI: Update LiveVariables · 0259a7aa
  Matt Arsenault authored Aug 15, 2015
  0259a7aa
- AMDGPU/SI: Update LiveIntervals during SIFixSGPRLiveRanges · 670ba46e
  Matt Arsenault authored Aug 15, 2015
  670ba46e
- AMDGPU: Remove unnecessary assert · b7523323
  Matt Arsenault authored Aug 15, 2015
  b7523323
- AMDGPU/SI: Make comments more precise. · 4275c29a
  Matt Arsenault authored Aug 15, 2015
  4275c29a
- Add a target environment for CoreCLR. · b399095c
  Pat Gavlin authored Aug 14, 2015
  b399095c