Commits · 82f0801c1b2baaee5479e0f8fd0840392958ef9b · Raul Torres / llvm-target-spread · GitLab

May 29, 2017
- [Nios2] Target registration · 82f0801c
  Nikolai Bozhenov authored May 29, 2017
  82f0801c
- [ARM] GlobalISel: Extract helper. NFCI. · 0c05cce4
  Diana Picus authored May 29, 2017
  0c05cce4
- [ARM] GlobalISel: Support array returns · bf4aed2c
  Diana Picus authored May 29, 2017
  bf4aed2c
- [PPC] Fix assertion failure during binary encoding with -mcpu=pwr9 · e3c14ebb
  Hiroshi Inoue authored May 29, 2017
  e3c14ebb
- [ARM] GlobalISel: Support array parameters/arguments · 8cca8cb0
  Diana Picus authored May 29, 2017
  8cca8cb0
- Resubmit "[X86] Adding new LLVM TableGen backend that generates the X86... · df1832cf
  Zachary Turner authored May 29, 2017
  df1832cf
- Revert "[X86] Adding new LLVM TableGen backend that generates the X86 backend... · 5b199be7
  Zachary Turner authored May 29, 2017
  5b199be7
- [AVR] Remove SREG from CPI's Uses; authored by Florian Zeitz · 74fc1ce0
  Dylan McKay authored May 29, 2017
  74fc1ce0
- [AArch64][Falkor] Combine sched details files into one. NFC. · 2739ebaf
  Geoff Berry authored May 28, 2017
  2739ebaf
May 28, 2017
- [AArch64][Falkor] Fix some sched details. · b542fb38
  Geoff Berry authored May 28, 2017
  b542fb38
- [X86] Adding new LLVM TableGen backend that generates the X86 backend memory folding tables. · d9f1fe43
  Ayman Musa authored May 28, 2017
  d9f1fe43
- [X86] Adding FoldGenRegForm helper field (for memory folding tables tableGen... · 0b4f97d5
  Ayman Musa authored May 28, 2017
  0b4f97d5
May 27, 2017
- AArch64/PEI: Do not add reserved regs to liveins · 88c8c984
  Matthias Braun authored May 27, 2017
  88c8c984
- [AArch64][GlobalISel] Add the Localizer pass for the O0 pipeline · 7a43eddf
  Quentin Colombet authored May 27, 2017
  7a43eddf
- AArch64: Fix cmpxchg O0 expansion · b4f74224
  Matthias Braun authored May 26, 2017
  b4f74224
- [bpf] disallow global_addr+off folding · 3c585d3a
  Alexei Starovoitov authored May 26, 2017
  3c585d3a
May 26, 2017
- [Mips] Placate GCC's -Wmisleading-indentation. NFCI. · ef9bfe95
  Davide Italiano authored May 26, 2017
  ef9bfe95
- LivePhysRegs: Rework constructor + documentation; NFC · ac4307c4
  Matthias Braun authored May 26, 2017
  ac4307c4
- [Hexagon] Cleanup of unused function isCalleeSaveReg (NFC) · a6cf2fd5
  Sumanth Gundapaneni authored May 26, 2017
  a6cf2fd5
- Resubmit r303859 with test fixed. · b2ff8dfe
  Konstantin Zhuravlyov authored May 26, 2017
  b2ff8dfe
- Make helper functions static. NFC. · debb3c35
  Benjamin Kramer authored May 26, 2017
  debb3c35
- [AMDGPU][MC][GFX9] Corrected encoding of flat_scratch* for SDWA opcodes · 6a2431df
  Dmitry Preobrazhensky authored May 26, 2017
  6a2431df
- AMDGPU/GlobalISel: Mark 32-bit float constants as legal · dde28a8c
  Tom Stellard authored May 26, 2017
  dde28a8c
- [AMDGPU] SDWA: add disassembler support for GFX9 · 363f47a2
  Sam Kolton authored May 26, 2017
  363f47a2
- [ARM] Fix lowering of misaligned memcpy/memset · 9009d290
  John Brawn authored May 26, 2017
  9009d290
- The fix for PR22004: X86AsmParser.cpp asserts: OperandStack.size() > 1 && "Too few operands." · fdb264e2
  Andrew V. Tischenko authored May 26, 2017
  fdb264e2
- Fix signedness of constant. NFC. · 6ff50bf2
  Nirav Dave authored May 26, 2017
  6ff50bf2
- [PPC] Add text for assert. · a76f20c3
  Tim Shen authored May 25, 2017
  a76f20c3
- [PPC] Fix atomics lowering in DAG lowering. · a2b85da8
  Tim Shen authored May 25, 2017
  a2b85da8
May 25, 2017
- PPC: Correct Size for GETtlsADDR · 13379d7c
  Kyle Butt authored May 25, 2017
  13379d7c
- Revert r303859, CodeGen/AMDGPU/llvm.amdgcn.s.getpc.ll fails on bots. · b3d83a09
  Nico Weber authored May 25, 2017
  b3d83a09
- [AArch64]: add 'a' inline asm operand modifier. · d536180f
  Manoj Gupta authored May 25, 2017
  d536180f
- [AMDGPU] add intrinsic for s_getpc · 32d0d386
  Tim Corringham authored May 25, 2017
  32d0d386
- [X86] Adding vpopcntd and vpopcntq instructions · 7bf27f03
  Oren Ben Simhon authored May 25, 2017
  7bf27f03
- [PowerPC] Fix a performance bug for PPC::XXSLDWI. · 0a429f04
  Tony Jiang authored May 24, 2017
  0a429f04
May 24, 2017
- [AArch64] Prevent nested ADDs from address calc in splitStoreSplat. NFC · bb20b5d5
  Nirav Dave authored May 24, 2017
  bb20b5d5
- P9: D-form vector load/store. Differential Revision: https://reviews.llvm.org/D33248 · 93297831
  Zaara Syeda authored May 24, 2017
  93297831
- Revert r291254: [AArch64] Reduce vector insert/extract cost for Falkor · 6349380f
  Matthew Simpson authored May 24, 2017
  6349380f
- [AMDGPU] Prevent too large store merges in AMDGPU Subtargets. NFCI. · d20066cb
  Nirav Dave authored May 24, 2017
  d20066cb
- [MSP430] Fix PR33050: Don't use ADD16ri to lower FrameIndex. · b07351f4
  Vadzim Dambrouski authored May 24, 2017
  b07351f4