Commits · 86eeda8e20d5aa5a5622a487c56364b4b26c6f3a · Raul Torres / llvm-target-spread · GitLab

Oct 01, 2016
- Revert "AMDGPU: Don't use offen if it is 0" · 86eeda8e
  Mehdi Amini authored Oct 01, 2016
  86eeda8e
- Remove TargetTriple from AArch64MCInstLower as it's used in few places · 98983d0a
  Eric Christopher authored Oct 01, 2016
  98983d0a
- AMDGPU: Don't use offen if it is 0 · 3070fdf7
  Matt Arsenault authored Oct 01, 2016
  3070fdf7
Sep 30, 2016
- [AArch64][RegisterBankInfo] Use the helper functions for the checks · a6119958
  Quentin Colombet authored Sep 30, 2016
  a6119958
- [AArch64][RegisterBankInfo] Rename getValueMappingIdx to getValueMapping · 7c3fa8e3
  Quentin Colombet authored Sep 30, 2016
  7c3fa8e3
- [AArch64][RegisterBankInfo] Compress the ValueMapping table a bit. · b4afac7b
  Quentin Colombet authored Sep 30, 2016
  b4afac7b
- [AArch64][RegisterBankInfo] Refactor the code to access AArch64::ValMapping · 7fc5fe41
  Quentin Colombet authored Sep 30, 2016
  7fc5fe41
- [AArch64][RegisterBankInfo] Rename getRegBankIdx to getRegBankIdxOffset · 15dc25bb
  Quentin Colombet authored Sep 30, 2016
  15dc25bb
- [AArch64][RegisterBankInfo] Use the static opds mapping for alt mappings · b2308987
  Quentin Colombet authored Sep 30, 2016
  b2308987
- X86: Allow conditional tail calls in Win64 "leaf" functions (PR26302) · b5643b47
  Hans Wennborg authored Sep 30, 2016
  b5643b47
- [WebAssembly] Make register stackification more conservative · e9e6891b
  Derek Schuff authored Sep 30, 2016
  e9e6891b
- [AMDGPU] Choose VMCNT, EXPCNT, LGKMCNT masks and shifts based on the isa version · 836cbff6
  Konstantin Zhuravlyov authored Sep 30, 2016
  836cbff6
- [AMDGPU] Ask subtarget if waitcnt instruction is needed before barrier instruction · d7bdf24f
  Konstantin Zhuravlyov authored Sep 30, 2016
  d7bdf24f
- [AMDGPU] Do not run scalar optimization passes at "-O0" · 4658e5f7
  Konstantin Zhuravlyov authored Sep 30, 2016
  4658e5f7
- [AVR] Add the ELF object file writer · 4a25499b
  Dylan McKay authored Sep 30, 2016
  4a25499b
- [AVR] Add the assembly instruction printer · 1a7bd84a
  Dylan McKay authored Sep 30, 2016
  1a7bd84a
- [AVX-512] Store address operand should be an input operand for the special... · f3e671e0
  Craig Topper authored Sep 30, 2016
  f3e671e0
- [AVX-512] Add the special stack spilling pseudos for XMM16-31 and YMM16-31... · 1c01cbe9
  Craig Topper authored Sep 30, 2016
  1c01cbe9
- Revert r282835 "[AVX-512] Always use the full 32 register vector classes for... · 3f37a418
  Craig Topper authored Sep 30, 2016
  3f37a418
- [X86] Add AVX-512 VTs to findRepresentativeClass as well as v16i16 which was... · de03ff70
  Craig Topper authored Sep 30, 2016
  de03ff70
- [AVX-512] Always use the full 32 register vector classes for addRegisterClass... · bc6e97b8
  Craig Topper authored Sep 30, 2016
  bc6e97b8
- AMDGPU: Use unsigned compare for eq/ne · 5d8eb25e
  Matt Arsenault authored Sep 30, 2016
  5d8eb25e
- [X86] Don't preserve Win64 SSE CSRs when SSE is disabled · 147f91c8
  Reid Kleckner authored Sep 30, 2016
  147f91c8
- [AArch64][RegisterBankInfo] Use static mapping for 3-operands instrs. · 4b36e0c4
  Quentin Colombet authored Sep 30, 2016
  4b36e0c4
- [AArch64][RegisterBankInfo] Add static value mapping for 3-op instrs. · fdd303af
  Quentin Colombet authored Sep 30, 2016
  fdd303af
- [AArch64][RegisterBankInfo] Check the statically created ValueMapping. · eb8d3da9
  Quentin Colombet authored Sep 30, 2016
  eb8d3da9
Sep 29, 2016
- [X86] Avoid "unused" warnings if no asserts · 3ace13ad
  Douglas Katzman authored Sep 29, 2016
  3ace13ad
- [X86][SSE] Added common helper for shuffle mask constant pool decodes. · 97a4820c
  Simon Pilgrim authored Sep 29, 2016
  97a4820c
- Revert "[AVR] Add instruction selection lowering code" · 7e91886a
  Dylan McKay authored Sep 29, 2016
  7e91886a
- [AVR] Add instruction selection lowering code · b79c01a4
  Dylan McKay authored Sep 29, 2016
  b79c01a4
- [AVX-512] Support spills of XMM16-31 and YMM16-31 when VLX isn't available. · d875d6b9
  Craig Topper authored Sep 29, 2016
  d875d6b9
- [AVX-512] Replicate pattern from AVX to select VMOVDDUP for (v2f64... · 7eb0e7ce
  Craig Topper authored Sep 29, 2016
  7eb0e7ce
- [X86] Add EVEX encoded VBROADCASTSS/SD and VPBROADCASTD/Q to execution domain fixing table. · e7f26111
  Craig Topper authored Sep 29, 2016
  e7f26111
- [X86] Remove AddedComplexity adjustments that don't seem to be needed. · cb3ae5a0
  Craig Topper authored Sep 29, 2016
  cb3ae5a0
- [X86] Add VBROADCASTF128/VBROADCASTI128 to execution domain fixing tables. · 816a1d77
  Craig Topper authored Sep 29, 2016
  816a1d77
- Remove an unnecessary duplicate initialization of TLOF from the Mips · 20ac9437
  Eric Christopher authored Sep 29, 2016
  20ac9437
- Update comment about initializing TLOF with a pointer at the previous · b4b75a53
  Eric Christopher authored Sep 29, 2016
  b4b75a53
- AMDGPU: Partially fix control flow at -O0 · e6740754
  Matt Arsenault authored Sep 29, 2016
  e6740754
- AArch64: Set shift bit of TLSLE HI12 add instruction · 361615cf
  Lei Liu authored Sep 29, 2016
  361615cf
- [RegisterBankInfo] Uniquely generate OperandsMapping. · 40cbc27f
  Quentin Colombet authored Sep 28, 2016
  40cbc27f