Commits · 932b992888e5cb602dd87c7650046adfe2343e01 · Raul Torres / llvm-target-spread · GitLab

Apr 03, 2012
- Add an option to turn off the expensive GVN load PRE part of GVN. · 932b9928
  Bill Wendling authored Apr 02, 2012
  932b9928
- Add predicates for checking whether targets have free FNEG and FABS... · 98f2c0c3
  Owen Anderson authored Apr 02, 2012
  98f2c0c3
Apr 02, 2012
- During two-address lowering, rescheduling an instruction does not untie · aaafacd0
  Lang Hames authored Apr 02, 2012
  aaafacd0
- No need to run llvm-as. · 2e5c58e7
  Rafael Espindola authored Apr 02, 2012
  2e5c58e7
- Initial 64 bit direct object support. · b1f68f96
  Akira Hatanaka authored Apr 02, 2012
  b1f68f96
- The binutils for the IBM BG/P are too old to support CFI. · 7591afa2
  Hal Finkel authored Apr 02, 2012
  7591afa2
- Add triple support for the IBM BG/P and BG/Q supercomputers. · f208af02
  Hal Finkel authored Apr 02, 2012
  f208af02
- Turn on the accelerator tables for Darwin. · ad9fe895
  Eric Christopher authored Apr 02, 2012
  ad9fe895
- Fast fix for PR12343: · f62ffeca
  Stepan Dyatkovskiy authored Apr 02, 2012
  f62ffeca
- Implement the SVR4 byval alignment for aggregates. Fixing a FIXME. · b9663ccd
  Roman Divacky authored Apr 02, 2012
  b9663ccd
- Second part for the 153874 one · 98144e9e
  Silviu Baranga authored Apr 02, 2012
  98144e9e
- Added fix in TableGen instruction decoder generation. The decoder now breaks for every leaf node. · ac37acd3
  Silviu Baranga authored Apr 02, 2012
  ac37acd3
- Add missing 'd'. · ebe09ec1
  Rafael Espindola authored Apr 02, 2012
  ebe09ec1
- Hack the hack. If we have a situation where an ASM object is defined but isn't · 71b19bbd
  Bill Wendling authored Apr 02, 2012
  71b19bbd
- Emit the asm writer's mnemonic table with SequenceToOffsetTable. · 22d093e4
  Benjamin Kramer authored Apr 02, 2012
  22d093e4
- Move getOpcodeName from the various target InstPrinters into the superclass MCInstPrinter. · 1c0541b0
  Benjamin Kramer authored Apr 02, 2012
  1c0541b0
- Reorder fields in MatchEntry and OperandMatchEntry to reduce padding. A bit... · 4de73738
  Craig Topper authored Apr 02, 2012
  4de73738
- Optimizing swizzles of complex shuffles may generate additional complex shuffles. · 702f0807
  Nadav Rotem authored Apr 02, 2012
  702f0807
- Remove getInstructionName from MCInstPrinter implementations in favor of using... · dab9e35a
  Craig Topper authored Apr 02, 2012
  dab9e35a
- Fix CXXFLAGS for huge_val.m4. · 8e52bdce
  Eric Christopher authored Apr 02, 2012
  8e52bdce
- Make MCInstrInfo available to the MCInstPrinter. This will be used to remove... · 54bfde79
  Craig Topper authored Apr 02, 2012
  54bfde79
- It could come about that we parse the inline ASM before we get a potential · 3a0bcf06
  Bill Wendling authored Apr 02, 2012
  3a0bcf06
- Use SequenceToOffsetTable to generate instruction name table for AsmWriter. · 7a2cea18
  Craig Topper authored Apr 02, 2012
  7a2cea18
- Start cleaning up the InlineCost class. This switches to sentinel values · 219173a1
  Chandler Carruth authored Apr 01, 2012
  219173a1
Apr 01, 2012
- Fix some 80-col. violations I introduced with the A2 PPC64 core. · 3ecfa7b2
  Hal Finkel authored Apr 01, 2012
  3ecfa7b2
- Enable prefetch generation on PPC64. · 322e41a9
  Hal Finkel authored Apr 01, 2012
  322e41a9
- Add LdStSTD* itin. for the PPC64 A2 core. · 9032344c
  Hal Finkel authored Apr 01, 2012
  9032344c
- This commit contains a few changes that had to go in together. · b0783508
  Nadav Rotem authored Apr 01, 2012
  b0783508
- Fix typo. · 652f2127
  Lang Hames authored Apr 01, 2012
  652f2127
- Set the default PPC node scheduling preference to ILP (for the embedded cores). · 88ed4e3b
  Hal Finkel authored Apr 01, 2012
  88ed4e3b
- Add ppc440 itin. entries for LdStSTD* · b9845f57
  Hal Finkel authored Apr 01, 2012
  b9845f57
- Use full anti-dep. breaking with post-ra sched. on the embedded ppc cores. · ec5a1e36
  Hal Finkel authored Apr 01, 2012
  ec5a1e36
- Add instruction itinerary for the PPC64 A2 core. · 9f9f8929
  Hal Finkel authored Apr 01, 2012
  9f9f8929
- Use SequenceToOffsetTable to create instruction name table. Saves space... · 91773ab2
  Craig Topper authored Apr 01, 2012
  91773ab2
- Emit the LLVM<->DWARF register mapping as a sorted table and use binary search to do the lookup. · 12af4285
  Benjamin Kramer authored Apr 01, 2012
  12af4285
- Belatedly address some code review from Chris. · 45ae88f5
  Chandler Carruth authored Apr 01, 2012
  45ae88f5
- Add some more testing to cover the remaining two cases where · cdb1f8cf
  Chandler Carruth authored Apr 01, 2012
  cdb1f8cf
- Fix a pretty scary bug I introduced into the always inliner with · c5bfb3c0
  Chandler Carruth authored Apr 01, 2012
  c5bfb3c0
- Replace four tiny tests with various uses of grep and not with a single · 1989bb9c
  Chandler Carruth authored Apr 01, 2012
  1989bb9c
- misched: Add finalizeScheduler to complete the target interface. · 779b32a4
  Andrew Trick authored Apr 01, 2012
  779b32a4