Commits · 9452ec722ce0ba356a5ad178b0b1964ba8efb534 · Raul Torres / llvm-target-spread · GitLab

Oct 02, 2021
- [X86][SSE] Fix typo + infinite-loop in HOP(HOP'(X,X),HOP'(Y,Y)) fold (PR52040) · 9452ec72
  Simon Pilgrim authored Oct 02, 2021
  9452ec72
- [X86] decomposeMulByConstant - decompose legal vXi32 multiplies on SlowPMULLD... · bb42cc20
  Simon Pilgrim authored Oct 01, 2021
  bb42cc20
- [X86] Atom SSE shift-by-variable take 2uops/3uops not 1uop · 8e7f6039
  Simon Pilgrim authored Sep 30, 2021
  8e7f6039
- [X86][Costmodel] Load/store i8 Stride=4 VF=32 interleaving costs · acb45957
  Roman Lebedev authored Oct 02, 2021
  acb45957
- [X86][Costmodel] Load/store i8 Stride=4 VF=16 interleaving costs · 0e71ae6d
  Roman Lebedev authored Oct 02, 2021
  0e71ae6d
- [X86][Costmodel] Load/store i8 Stride=4 VF=8 interleaving costs · 74e4a0e3
  Roman Lebedev authored Oct 02, 2021
  74e4a0e3
- [X86][Costmodel] Load/store i8 Stride=4 VF=4 interleaving costs · ae08362c
  Roman Lebedev authored Oct 02, 2021
  ae08362c
- [X86][Costmodel] Load/store i8 Stride=4 VF=2 interleaving costs · 935b9693
  Roman Lebedev authored Oct 02, 2021
  935b9693
- [X86][Costmodel] Load/store i8 Stride=3 VF=32 interleaving costs · 448c9398
  Roman Lebedev authored Oct 02, 2021
  448c9398
- [X86][Costmodel] Load/store i8 Stride=3 VF=8 interleaving costs · d1460c88
  Roman Lebedev authored Oct 02, 2021
  d1460c88
- [X86][Costmodel] Load/store i8 Stride=3 VF=4 interleaving costs · f1df2d8e
  Roman Lebedev authored Oct 02, 2021
  f1df2d8e
- [X86][Costmodel] Load/store i8 Stride=3 VF=2 interleaving costs · 8a3c64c3
  Roman Lebedev authored Oct 02, 2021
  8a3c64c3
- [llvm-cxxfilt] Replace isalnum with isAlnum from StringExtras · f33274c7
  Tomasz Miąsko authored Oct 02, 2021
  f33274c7
- [AArch64][GlobalISel] Lower G_SMULH/G_UMULH unless its one of the supported types. · f41a9cf8
  Amara Emerson authored Oct 01, 2021
  f41a9cf8
- [DWARF][NFC] add ParentIdx and SiblingIdx to DWARFDebugInfoEntry for faster navigation. · 0b8c5081
  Alexey Lapshin authored Sep 23, 2021
  0b8c5081
- [gn build] Port 657f02d4 · e420164f
  LLVM GN Syncbot authored Oct 02, 2021
  
  e420164f
- Revert "Extract LC_CODE_SIGNATURE related implementation out of LLD" · 657f02d4
  Daniel Rodríguez Troitiño authored Oct 01, 2021
  657f02d4
- [test] add coverage for a SCEVUnknown scoped value in isSCEVExprNeverPoison · 91dfc084
  Philip Reames authored Oct 01, 2021
  91dfc084
- [SCEV] Stop blindly propagating flags from inbound geps to SCEV nodes · 2ca8a3f2
  Philip Reames authored Oct 01, 2021
  2ca8a3f2
- [SCEV] Remove invariant requirement from isSCEVExprNeverPoison · 24cde2f6
  Philip Reames authored Oct 01, 2021
  24cde2f6
- [test] split flags-from-poison.ll to allow ease of autogen update · d0bca006
  Philip Reames authored Oct 01, 2021
  
  d0bca006
- [AArch64][GlobalISel] Change G_ANYEXT fed by scalar G_ICMP to G_ZEXT · 96843d22
  Jessica Paquette authored Oct 01, 2021
  96843d22
Oct 01, 2021
- [NFC][PowerPC] Add test case for byval store. · 40f382ad
  Stefan Pintilie authored Oct 01, 2021
  40f382ad
- Revert "[DomTree] Assert that blocks in queries aren't from another function" · a67c7dea
  Daniil Suchkov authored Oct 01, 2021
  a67c7dea
- [DomTree] Assert that blocks in queries aren't from another function · 86046516
  Daniil Suchkov authored Sep 28, 2021
  86046516
- [SimpleLoopUnswitch] Don't unswitch constant conditions · 45bd8d94
  Daniil Suchkov authored Sep 28, 2021
  45bd8d94
- [Test] Add a test exposing a miscompile in SimpleLoopUnswitch. · bdd52e8b
  Daniil Suchkov authored Sep 28, 2021
  bdd52e8b
- [BasicAA] Make test more robust (NFC) · b084b98a
  Nikita Popov authored Oct 01, 2021
  b084b98a
- [BasicAA] Add additional truncation tests (NFC) · b7ff0489
  Nikita Popov authored Oct 01, 2021
  b7ff0489
- [gn build] Port c8c2b462 · 4cdee8de
  LLVM GN Syncbot authored Oct 01, 2021
  
  4cdee8de
- [Demangle][Rust] Parse non-ASCII identifiers · c8c2b462
  Tomasz Miąsko authored Oct 01, 2021
  c8c2b462
- [DAG] scalarizeExtractedVectorLoad - replace getABITypeAlign with allowsMemoryAccess (PR45116) · df672f66
  Simon Pilgrim authored Oct 01, 2021
  df672f66
- [TwoAddressInstruction] Tweak constraining of tied operands · dff3454b
  Jay Foad authored Oct 01, 2021
  dff3454b
- [TwoAddressInstruction] Pre-commit a test case for D110944 · 61ecfc6f
  Jay Foad authored Oct 01, 2021
  
  61ecfc6f
- [NFC][X86][Codegen] Add test coverage for interleaved i8 load/store stride=4 · 3c407196
  Roman Lebedev authored Oct 01, 2021
  
  3c407196
- [NFC][X86][LV] Improve costmodel test coverage for interleaved i8 load/store stride=4 · 53d7bdbf
  Roman Lebedev authored Oct 01, 2021
  
  53d7bdbf
- [BasicAA] Add additional 32-bit truncation test (NFC) · 04a6f80e
  Nikita Popov authored Oct 01, 2021
  04a6f80e
- [ORC] Fix LLVM modulemap after removal of ORC RPC in 33dd98e9 . · 00e23067
  Lang Hames authored Oct 01, 2021
  
  00e23067
- [InstCombine] fold (trunc (X>>C1)) << C to shift+mask directly · 3fabd98e
  Sanjay Patel authored Oct 01, 2021
  3fabd98e
- [gn build] Port 33dd98e9 · 06cea95a
  LLVM GN Syncbot authored Oct 01, 2021
  
  06cea95a