Commits · cb8f6328dc6e81b2f572e15f9d28be5c8c233655 · Raul Torres / llvm-target-spread · GitLab

Oct 24, 2017
- [NVPTX] allow address space inference for volatile loads/stores. · cb8f6328
  Artem Belevich authored Oct 24, 2017
  cb8f6328
- [X86][Broadwell] Added the instruction scheduling information for the Broadwell CPU. · 323f2e17
  Gadi Haber authored Oct 24, 2017
  323f2e17
- bpf: fix a bug in trunc-op optimization · ee68d8e4
  Yonghong Song authored Oct 24, 2017
  ee68d8e4
- [PowerPC] Try to simplify a Swap if it feeds a Splat · 8f0c7830
  Stefan Pintilie authored Oct 24, 2017
  8f0c7830
- bpf: fix a bug in bpf-isel trunc-op optimization · 0f836d5d
  Yonghong Song authored Oct 24, 2017
  0f836d5d
- [X86][AVX] ComputeNumSignBitsForTargetNode - add support for X86ISD::VTRUNC · 5e8c3f32
  Simon Pilgrim authored Oct 24, 2017
  5e8c3f32
- PowerPC: support the separator character in the IAS · fb490a0b
  Saleem Abdulrasool authored Oct 24, 2017
  fb490a0b
- [X86] truncateVectorCompareWithPACKSS - use PACKSSDW/PACKSSWB instead of just PACKSSWB. · 0a12c239
  Simon Pilgrim authored Oct 24, 2017
  0a12c239
- [ARM] Error for invalid shift in memory operand · 03ded27b
  Oliver Stannard authored Oct 24, 2017
  03ded27b
- [X86] truncateVectorCompareWithPACKSS - remove duplicate variables. NFCI. · c36dd6ae
  Simon Pilgrim authored Oct 24, 2017
  c36dd6ae
- Update f16c instruction scheduling on btver2. · f4fbe4a5
  Andrew V. Tischenko authored Oct 24, 2017
  f4fbe4a5
- X86CallFrameOptimization: Update comments and variable names. NFCI. · bf31bf78
  Zvi Rackover authored Oct 24, 2017
  bf31bf78
- X86CallFrameOptimization: Recognize 'store 0/-1 using and/or' idioms · 31b101a1
  Zvi Rackover authored Oct 24, 2017
  31b101a1
- AMDGPU: Add new intrinsic llvm.amdgcn.kill(i1) · ce76ea03
  Marek Olsak authored Oct 24, 2017
  ce76ea03
- AMDGPU: Add llvm.amdgcn.wqm.vote intrinsic · 2114fc3b
  Marek Olsak authored Oct 24, 2017
  2114fc3b
- [ARM] Replace development diagnostics with normal DEBUG macro · ce256a3a
  Oliver Stannard authored Oct 24, 2017
  ce256a3a
- [ARM] tSETEND needs IsThumb · 6d5a5b98
  Oliver Stannard authored Oct 24, 2017
  6d5a5b98
- [ARM] Remove tCPS alias which just crashed · c507b370
  Oliver Stannard authored Oct 24, 2017
  c507b370
- X86: Fix X86CallFrameOptimization to search for the COPY StackPointer · 3c0d3855
  Zvi Rackover authored Oct 24, 2017
  3c0d3855
- [MC] Adding code padding for performance stability - infrastructure. NFC. · 2251c79a
  Omer Paparo Bivas authored Oct 24, 2017
  2251c79a
- X86: Register the X86CallFrameOptimization pass · c6d0b6c1
  Zvi Rackover authored Oct 24, 2017
  c6d0b6c1
- AMDGPU: Initialize WavefrontSize from TD files · 339e7444
  Konstantin Zhuravlyov authored Oct 23, 2017
  339e7444
- [X86][SSE] combineBitcastvxi1 - use PACKSSWB directly to pack v8i16 to v16i8 · 321e54f7
  Simon Pilgrim authored Oct 23, 2017
  321e54f7
Oct 23, 2017
- Revert "[PowerPC] Try to simplify a Swap if it feeds a Splat" · 52bbd587
  Stefan Pintilie authored Oct 23, 2017
  52bbd587
- [Hexagon] Return the correct chain edge for i1 function calls · 6f06b6ed
  Krzysztof Parzyszek authored Oct 23, 2017
  6f06b6ed
- [PowerPC] Try to simplify a Swap if it feeds a Splat · feafa1d7
  Stefan Pintilie authored Oct 23, 2017
  feafa1d7
- [Hexagon] Add extra pattern for S4_addaddi · 27367882
  Krzysztof Parzyszek authored Oct 23, 2017
  27367882
- [globalisel][tablegen] Import stores and allow GISel to automatically... · d66e0901
  Daniel Sanders authored Oct 23, 2017
  d66e0901
- AMDGPU: Cleanup local atomic node names · a030e268
  Matt Arsenault authored Oct 23, 2017
  a030e268
- AMDGPU: Fix default range in non-kernel functions · b791802a
  Matt Arsenault authored Oct 23, 2017
  b791802a
- [X86] Change VMPTRST to use PS instead of TB to match VMPTRLD. · 8d5a246e
  Craig Topper authored Oct 23, 2017
  8d5a246e
- [X86] Change RDRAND to use PS instead of TB. · 1db2f082
  Craig Topper authored Oct 23, 2017
  1db2f082
- [X86] Change XRSTOR to use PS instead of TB to match XSAVE. · 4d93adfe
  Craig Topper authored Oct 23, 2017
  4d93adfe
- [X86][SSE] Remove AssertZext stage from PEXTRW/PEXTRB lowering. NFCI. · 1dcb913b
  Simon Pilgrim authored Oct 23, 2017
  1dcb913b
- Update DPPD/DPPS instruction scheduling on btver2. · 777308b5
  Andrew V. Tischenko authored Oct 23, 2017
  777308b5
- [X86] Add PTWRITE instruction for assembler and disassembler. · 8f182fdd
  Craig Topper authored Oct 23, 2017
  8f182fdd
- [X86] Add RDPID instruction for assembler and disassembler. · 5f0339d2
  Craig Topper authored Oct 23, 2017
  5f0339d2
- Fix for Bug 30718 - Failure to disassemble certain MOV with rex.R. The issue... · eff4fc0d
  Andrew V. Tischenko authored Oct 23, 2017
  eff4fc0d
- Fix a -Wpedantic warning. · 1afddd41
  Haojian Wu authored Oct 23, 2017
  1afddd41
- [ARM] Allow unrolling of multi-block loops. · 487ab869
  Sam Parker authored Oct 23, 2017
  487ab869