Commits · fa496ce3c6774097080c8a9cb808da56f383b938 · Raul Torres / llvm-target-spread · GitLab

Mar 30, 2020
- [Intrinsic] Give "is.constant" the "convergent" attribute · fa496ce3
  Bill Wendling authored Mar 30, 2020
  fa496ce3
- GlobalISel: Translate llvm.fshl/llvm.fshr · 23da702d
  Matt Arsenault authored Mar 19, 2020
  
  23da702d
- [AMDGPU] Add Relocation Constant Support · 77ce2e21
  Jakub Kuderski authored Mar 30, 2020
  77ce2e21
- Introduce unify-loop-exits pass. · 3cbbded6
  Sameer Sahasrabuddhe authored Mar 28, 2020
  3cbbded6
- [LoopVectorize] Fix crash on "getNoopOrZeroExtend cannot truncate!" (PR45259) · dcc410b5
  Vedant Kumar authored Mar 30, 2020
  dcc410b5
- [X86] make sure POP has implicit def/use of stack pointer when materializing... · ece79f47
  Yuanfang Chen authored Mar 29, 2020
  ece79f47
- AMDGPU/GlobalISel: Hack to fix i24 argument lowering · bb009498
  Matt Arsenault authored Mar 21, 2020
  bb009498
- AMDGPU/GlobalISel: Legalize 64-bit G_UDIV/G_UREM · 90a36bbd
  Matt Arsenault authored Feb 26, 2020
  90a36bbd
- [DebugInfo] Ensure that a demanded bits optimisation in · f6b2c003
  Chris Jackson authored Mar 30, 2020
  f6b2c003
- Revert "[Darwin] Respect -fno-unroll-loops during LTO." · 7899a111
  Florian Hahn authored Mar 30, 2020
  7899a111
- [DebugInfo] Ensure dead store elimination can mark an operand · 135709aa
  Chris Jackson authored Mar 30, 2020
  135709aa
- [InstCombine] add test for trunc-extelt; NFC · bc60cdcc
  Sanjay Patel authored Mar 30, 2020
  bc60cdcc
- [llvm-readobj] - Improve test of --elf-hash-histogram option. · 4cbfb98e
  Georgii Rymar authored Mar 27, 2020
  4cbfb98e
- [llvm-readobj][test] - Simplify hash-symbols test. · 821439a4
  Georgii Rymar authored Mar 27, 2020
  821439a4
- [X86][AVX] lowerV4X128Shuffle - attempt to widen to 2x256 to simplify shuffles · e95d04f4
  Simon Pilgrim authored Mar 30, 2020
  e95d04f4
- [CVP] Add additional icmp for ranges with undef to test. · 84c1fbab
  Florian Hahn authored Mar 29, 2020
  
  84c1fbab
- [NFC] [PowerPC] Update and add tests for ori · 9aa884cc
  Qiu Chaofan authored Mar 30, 2020
  9aa884cc
- [ARM][LowOverheadLoops] Add horizontal reduction support · 94b195ff
  Sam Parker authored Mar 30, 2020
  94b195ff
- [ARM] MVE VMOV.i64 · c9eaed51
  David Green authored Mar 28, 2020
  c9eaed51
- [TTI][X86] Fix the value passed to IsUnsigned for cost modeling of... · b4695351
  Craig Topper authored Mar 29, 2020
  b4695351
- [Coroutines 2/2] Improve symmetric control transfer feature · 31a1d85c
  Jun Ma authored Mar 27, 2020
  31a1d85c
- [Coroutines 1/2] Improve symmetric control transfer feature · a94fa2c0
  Jun Ma authored Mar 27, 2020
  a94fa2c0
- [X86] Add sse4.1 RUNs lines to the min/max reduction cost model tests. · d74533a1
  Craig Topper authored Mar 29, 2020
  d74533a1
Mar 29, 2020
- [InstCombine] Add tests for trunc (extelt x); (NFC) · 24562c65
  Daan Sprenkels authored Mar 29, 2020
  24562c65
- [X86] Add sse4.2 command lines to min/max reduction tests. · 2451e4c5
  Craig Topper authored Mar 29, 2020
  2451e4c5
- [ARM] VMOV.64 immediate tests. NFC · 7c1a6873
  David Green authored Mar 28, 2020
  
  7c1a6873
- [X86][AVX] Combine 128/256-bit lane shuffles with zeroable upper subvectors to... · 9c8ec99c
  Simon Pilgrim authored Mar 29, 2020
  9c8ec99c
- Introduce support for lib function aligned_alloc in TLI / memory builtins · c0955edf
  Uday Bondhugula authored Mar 28, 2020
  c0955edf
- AMDGPU: Add some additional tests for v_cvt_ubyte* formation · 0b68ca51
  Matt Arsenault authored Mar 29, 2020
  0b68ca51
- [InstCombine] make test independent of branch undef/UB; NFC · febcb24f
  Sanjay Patel authored Mar 29, 2020
  
  febcb24f
- [X86][AVX] Add tests for 512-bit shuffle patterns that could reduce to subvector extractions · 443dcc0e
  Simon Pilgrim authored Mar 29, 2020
  
  443dcc0e
- Remove unnecessary empty comments from test check lines. NFC. · b44f0704
  Simon Pilgrim authored Mar 29, 2020
  
  b44f0704
- [X86][AVX] Combine 128-bit lane shuffles with a zeroable upper half to EXTRACT_SUBVECTOR (PR40720) · 7734e4b3
  Simon Pilgrim authored Mar 29, 2020
  7734e4b3
- [X86][AVX] Add X86ISD::VALIGN target shuffle decode support · 10439f9e
  Simon Pilgrim authored Mar 29, 2020
  10439f9e
- [X86] X86CallFrameOptimization - generalize slow push code path · a7115d51
  Simon Pilgrim authored Mar 29, 2020
  a7115d51
- [AlignmentFromAssumptions] Fix a SCEV assertion resulting from address space differences. · 4bf015c0
  Richard Diamond authored Mar 02, 2020
  4bf015c0
- [X86] Add cost model test cases for fmin/fmax reduction. · c0aa97b6
  Craig Topper authored Mar 28, 2020
  
  c0aa97b6
- [MC][PowerPC] Make .reloc support arbitrary relocation types · fc93787d
  Fangrui Song authored Mar 28, 2020
  fc93787d
Mar 28, 2020
- [BPF] support 128bit int explicitly in layout spec · ced0d1f4
  Yonghong Song authored Mar 21, 2020
  ced0d1f4
- [CodeGen] Fix sinking local values in lpads with phis · e5bf5037
  Reid Kleckner authored Mar 28, 2020
  e5bf5037