Commits · fc50498ced7f85279b901fce302d01e558c74c7d · Raul Torres / llvm-target-spread · GitLab

Jul 18, 2018
- CodeGen: Don't create address significance table entries for thread-local variables. · fc50498c
  Peter Collingbourne authored Jul 18, 2018
  fc50498c
- [X86] Remove the vector alignment requirement from the patterns added in r337320. · a29f58dc
  Craig Topper authored Jul 17, 2018
  a29f58dc
- CodeGen: Add a target option for emitting .addrsig directives for all address-significant symbols. · bd9d313d
  Peter Collingbourne authored Jul 17, 2018
  bd9d313d
Jul 17, 2018
- [X86] Add patterns for folding full vector load into MOVHPS and MOVLPS with SSE1 only. · 9ef92865
  Craig Topper authored Jul 17, 2018
  9ef92865
- [X86] Add test case for missed opportunity to use MOVLPS on the SSE1 only targets. · c0f2e306
  Craig Topper authored Jul 17, 2018
  c0f2e306
- [x86/SLH] Flesh out the data-invariant instruction table a bit based on feedback from Craig. · c0cb5731
  Chandler Carruth authored Jul 17, 2018
  c0cb5731
- [WebAssembly] Update WebAssemblyLowerEmscriptenEHSjLj to handle separate compilation · 28b3e994
  Sam Clegg authored Jul 17, 2018
  28b3e994
- [Mips][FastISel] Fix handling of icmp with i1 type · f10e4798
  Petar Jovanovic authored Jul 17, 2018
  f10e4798
- More fixes for subreg join failure in RegCoalescer · e1016f1b
  Tim Renouf authored Jul 17, 2018
  e1016f1b
- [DAGCombiner] Call SimplifyDemandedVectorElts from EXTRACT_VECTOR_ELT · e4d12bb2
  Simon Pilgrim authored Jul 17, 2018
  e4d12bb2
- [Sparc] Do not depend on icc for ta 1 · c812dcc3
  Daniel Cederman authored Jul 17, 2018
  c812dcc3
- [X86] Add full set of patterns for turning ceil/floor/trunc/rint/nearbyint... · c376a191
  Craig Topper authored Jul 17, 2018
  c376a191
- [X86] Add test cases for selecting floor/ceil/trunc/rint/nearbyint to rndscale... · c89ef8b1
  Craig Topper authored Jul 17, 2018
  c89ef8b1
- [X86] Add a missing FMA3 scalar intrinsic pattern. · 6751727d
  Craig Topper authored Jul 16, 2018
  6751727d
- [Intrinsics] define funnel shift IR intrinsics + DAG builder support · c71adc80
  Sanjay Patel authored Jul 16, 2018
  c71adc80
Jul 16, 2018
- [AMDGPU] [AMDGPU] Support a fdot2 pattern. · c370d7b3
  Farhana Aleen authored Jul 16, 2018
  c370d7b3
- [RegAlloc] Skip global splitting if the live range is huge and its spill is · 40c4aa76
  Wei Mi authored Jul 16, 2018
  40c4aa76
- [x86/SLH] Completely rework how we sink post-load hardening past data · fa065aa7
  Chandler Carruth authored Jul 16, 2018
  fa065aa7
- [MIPS GlobalISel] Select instructions to load and store i32 on stack · 021e4c82
  Petar Jovanovic authored Jul 16, 2018
  021e4c82
- [X86][AArch64][DAGCombine] Unfold 'check for [no] signed truncation' pattern · de506632
  Roman Lebedev authored Jul 16, 2018
  de506632
- [Sparc] Use the correct encoding for ta 3 · 92a700a2
  Daniel Cederman authored Jul 16, 2018
  92a700a2
- [Sparc] Use the names .rem and .urem instead of __modsi3 and __umodsi3 · ab09da7b
  Daniel Cederman authored Jul 16, 2018
  ab09da7b
- [Sparc] Generate ta 1 for the @llvm.debugtrap intrinsic · 68765757
  Daniel Cederman authored Jul 16, 2018
  68765757
- Avoid losing Hi part when expanding VAARG nodes on big endian machines · c3d8002c
  Daniel Cederman authored Jul 16, 2018
  c3d8002c
- [x86/SLH] Fix a bug where we would try to post-load harden non-GPRs. · e66a6f48
  Chandler Carruth authored Jul 16, 2018
  e66a6f48
- run post-RA hazard recognizer pass late · 72da47df
  Mark Searles authored Jul 16, 2018
  72da47df
- [X86] Merge the FR128 and VR128 regclass since they have identical spill and... · 07a17875
  Craig Topper authored Jul 16, 2018
  07a17875
- [x86/SLH] Teach speculative load hardening to correctly harden the · cdf0addc
  Chandler Carruth authored Jul 16, 2018
  cdf0addc
- [X86] Add custom execution domain fixing for 128/256-bit integer logic... · cdb0ed29
  Craig Topper authored Jul 15, 2018
  cdb0ed29
Jul 15, 2018
- [X86] Use 128-bit blends instead vmovss/vmovsd for 512-bit vzmovl patterns to match AVX. · ec003839
  Craig Topper authored Jul 15, 2018
  ec003839
- [X86] Use 128-bit ops for 256-bit vzmovl patterns. · 8f348587
  Craig Topper authored Jul 15, 2018
  8f348587
- [DAGCombiner] extend(ifpositive(X)) -> shift-right (not X) · a41c886c
  Sanjay Patel authored Jul 15, 2018
  a41c886c
- [AMDGPU] adjusted test checks because minnum with NaN gets simplified · 810f51ec
  Sanjay Patel authored Jul 15, 2018
  810f51ec
- [X86] Add some optsize patterns for 256-bit X86vzmovl. · 60ce8561
  Craig Topper authored Jul 15, 2018
  60ce8561
Jul 14, 2018
- [MachineOutliner] Check the last instruction from the sequence when updating liveness · f905bf14
  Francis Visoiu Mistrih authored Jul 14, 2018
  f905bf14
- [x86/SLH] Fix an issue where we wouldn't harden any loads if we found · fb503ac0
  Chandler Carruth authored Jul 14, 2018
  fb503ac0
- [X86] Fix a subtle bug in the custom execution domain fixing for blends. · 7426cf67
  Craig Topper authored Jul 14, 2018
  7426cf67
- [X86] Prefer blendi over movss/sd when avx512 is enabled unless optimizing for size. · f0b16441
  Craig Topper authored Jul 14, 2018
  f0b16441
- Revert "AMDGPU: Fix handling of alignment padding in DAG argument lowering" · 1971ba09
  Evgeniy Stepanov authored Jul 14, 2018
  1971ba09
- Add a CHECK line for r337072. · e78bd281
  Tim Shen authored Jul 13, 2018
  e78bd281