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Commit 0a0d2f54 authored by Simon Pilgrim's avatar Simon Pilgrim
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[X86] Ensure 256-bit inlane shuffles are set to 2 uops + half rate

znver1 double pumps regular 256-bit shuffles (crosslane shuffles are messier....)

Fixes yet another mismatch between the numbers coming out of the script from D103695 and the znver1 scheduler model

Confirmed with the AMD SoG, Agner + instlatx64
parent c4dd260f
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