Commits · 061e071d8c9b98526f35cad55a918a4f1615afd4 · Lorenzo Albano / LLVM bpEVL · GitLab

May 11, 2021
- Revert "[lld][WebAssembly] Initial support merging string data" · 061e071d
  Nico Weber authored May 10, 2021
  061e071d
- [AArch64][GlobalISel] Enable memcpy family combines on minsize functions · 6d8b070d
  Jessica Paquette authored May 10, 2021
  6d8b070d
May 10, 2021
- [Hexagon] Handle loads and stores of scalar predicate vectors · 8b9c15c2
  Krzysztof Parzyszek authored May 10, 2021
  8b9c15c2
- [X86] AMD Zen 3: same-reg AVX YMM VPCMP is dep breaking one-idiom · 6a64c462
  Roman Lebedev authored May 10, 2021
  6a64c462
- [X86] AMD Zen 3: same-reg AVX XMM VPCMP is dep breaking one-idiom · 29532453
  Roman Lebedev authored May 10, 2021
  29532453
- [X86] AMD Zen 3: same-reg SSE XMM PCMP is dep breaking one-idiom · 0f3bcb97
  Roman Lebedev authored May 10, 2021
  0f3bcb97
- [X86] AMD Zen 3: same-reg PCMPEQ is an MMX all-ones dep breaking idiom · b24edfff
  Roman Lebedev authored May 10, 2021
  b24edfff
- [lld][WebAssembly] Initial support merging string data · 5000a1b4
  Sam Clegg authored Feb 26, 2021
  5000a1b4
- [PowerPC] Spilling to registers does not require frame index scavenging · 6215f49b
  Stefan Pintilie authored May 10, 2021
  6215f49b
- [X86] AMD Zen 3: sub-32-bit CMP also break dependencies · 08cf2776
  Roman Lebedev authored May 10, 2021
  08cf2776
- [X86][SSE] canonicalizeShuffleMaskWithHorizOp - add TODO for better... · e32374ed
  Simon Pilgrim authored May 10, 2021
  e32374ed
- [RISCV] Correct VL for fixed length masked scatter. · 80b95108
  Craig Topper authored May 10, 2021
  80b95108
- [clang][AArch32] Correctly align HA arguments when passed on the stack · 5c7b43aa
  Momchil Velikov authored May 10, 2021
  5c7b43aa
- [PowerPC] Enable safe for 32bit vins* P10 instructions · 0c41f778
  Zarko Todorovski authored May 10, 2021
  0c41f778
- [AArch64][SVE] Improve SVE codegen for fixed length BITCAST · 635164b9
  Bradley Smith authored May 06, 2021
  635164b9
- X86FlagsCopyLowering.cpp - try to pass DebugLoc by const-ref to avoid costly... · 605f9047
  Simon Pilgrim authored May 10, 2021
  605f9047
- X86LoadValueInjectionLoadHardening.cpp - use const-reference in for-range... · 9243a584
  Simon Pilgrim authored May 10, 2021
  9243a584
- [AArch64][SVE] Better utilisation of unpredicated forms of remaining intrinsics · 65c89cd1
  Bradley Smith authored Apr 30, 2021
  65c89cd1
- [AArch64][SVE] Better utilisation of unpredicated forms of arithmetic intrinsics · f8f953c2
  Bradley Smith authored Apr 30, 2021
  f8f953c2
- [AArch64][SVE] Fix isel failure for FP-extending loads · 407a3388
  Sander de Smalen authored May 10, 2021
  407a3388
- HexagonVectorCombine.cpp - don't negate a bool value. NFCI. · ea64200b
  Simon Pilgrim authored May 10, 2021
  ea64200b
- AMDGPU/GlobalISel: Use destination register bank in applyMappingLoad · f6985a19
  Petar Avramovic authored May 10, 2021
  f6985a19
- [LegalizeVectorOps][RISCV] Add scalable-vector SELECT expansion · 6db0cedd
  Fraser Cormack authored May 07, 2021
  6db0cedd
- [AArch64][SVE] Remove index_vector node. · b3aeb138
  Jun Ma authored Apr 30, 2021
  b3aeb138
- [RISCV][NFC] Don't need to create a new STI in RISCVAsmPrinter. · 446ed639
  Zakk Chen authored May 05, 2021
  446ed639
May 09, 2021
- [X86] AMD Zen 3: same-reg CMP is a zero-cycle dependency-breaking instruction · be23d5e8
  Roman Lebedev authored May 09, 2021
  be23d5e8
- [X86] AMD Zen 3: same-reg SBB is a dependency-breaking instruction · 11b0568d
  Roman Lebedev authored May 09, 2021
  11b0568d
- [X86] AMD Zen 3: same-register XOR/SUB are GPR dependency breaking zero-idioms · eed85527
  Roman Lebedev authored May 09, 2021
  eed85527
- [ARM] Fix postinc of vst1xN · 76786037
  David Green authored May 09, 2021
  76786037
- [NFC][X86] Znver3: drop obsolete fixme · 675daef5
  Roman Lebedev authored May 09, 2021
  
  675daef5
- [X86] AMD Zen 3: XCHG is a zero-cycle instruction · a21df76d
  Roman Lebedev authored May 09, 2021
  a21df76d
- [NFCI][X86] Mark Znver3 scheduling model as complete · f8589292
  Roman Lebedev authored May 08, 2021
  f8589292
- [NFCI][X86] Mark a few lately-added system instructions as such for Scheduling purposes · d5494931
  Roman Lebedev authored May 08, 2021
  
  d5494931
May 08, 2021
- [Hexagon] Propagate metadata in Hexagon Vector Combine · 56102693
  Krzysztof Parzyszek authored May 07, 2021
  
  56102693
- [X86] combineHorizOpWithShuffle - generalize HOP(SHUFFLE(X),SHUFFLE(Y)) -> SHUFFLE(HOP(X,Y)) fold. · 4524d8b7
  Simon Pilgrim authored May 08, 2021
  4524d8b7
- [X86] Improve costmodel for scalar byte swaps · b1c38207
  Roman Lebedev authored May 08, 2021
  b1c38207
- [X86] Support AMX fast register allocation · d4bdeca5
  Xiang1 Zhang authored May 08, 2021
  d4bdeca5
- Revert "[X86] Support AMX fast register allocation" · bebafe01
  Xiang1 Zhang authored May 08, 2021
  bebafe01
- [X86] Support AMX fast register allocation · 77e2e5e0
  Xiang1 Zhang authored May 07, 2021
  
  77e2e5e0
- [NewPM] Hide pass manager debug logging behind -debug-pass-manager-verbose · 34a8a437
  Arthur Eubanks authored May 03, 2021
  34a8a437