Commits · 246d10609410a2ab2ea3309a88d16cdce8ce6f53 · Lorenzo Albano / LLVM bpEVL · GitLab

Jun 09, 2020
- [PowerPC] Fix pattern for DCBFL/DCBFLP instrinsics. · 246d1060
  Anil Mahmud authored Jun 08, 2020
  246d1060
- [PowerPC] Remove extra instruction left by emitRLDICWhenLoweringJumpTables · c9790d54
  Anil Mahmud authored Jun 08, 2020
  c9790d54
- [PowerPC] Fix incorrect PC Relative relocations for Big Endian · b4036329
  Stefan Pintilie authored Jun 08, 2020
  b4036329
- [AArch64] Support expression results as immediate values in mov · 0e1accd0
  Jian Cai authored Jun 08, 2020
  0e1accd0
- [AMDGPU][NFC] Skip processing intrinsics that do not become real instructions · 6a31a9a5
  dfukalov authored Jun 06, 2020
  6a31a9a5
- Revert "[arm][darwin] Don't generate libcalls for wide shifts on Darwin" · 7e58d0de
  Eli Friedman authored Jun 08, 2020
  7e58d0de
- [InstrProfiling] Use !associated metadata for counters, data and values · 603d58b5
  Petr Hosek authored Jul 13, 2019
  603d58b5
Jun 08, 2020
- Revert "[InstrProfiling] Use !associated metadata for counters, data and values" · ba10bedf
  Petr Hosek authored Jun 08, 2020
  ba10bedf
- Stabilize alloca slices sort in SROA · 87ff3401
  Stanislav Mekhanoshin authored Jun 08, 2020
  87ff3401
- [DebugInfo] Fix assertion for extern void type · 3eb465a3
  Yonghong Song authored Jun 05, 2020
  3eb465a3
- [InstrProfiling] Use !associated metadata for counters, data and values · 39b3c41b
  Petr Hosek authored Jul 13, 2019
  39b3c41b
- [XCOFF][AIX] report_fatal_error when an overflow section is needed · 775ef445
  jasonliu authored Jun 08, 2020
  775ef445
- [AArch64] Fix ldst-opt of multiple disjunct subregs. · 1975ff9a
  Florian Hahn authored Jun 08, 2020
  1975ff9a
- [PGO] CallPromotion: Don't try to pass sret args to varargs functions · fc202c5f
  Hans Wennborg authored Jun 08, 2020
  fc202c5f
- [X86] Prevent LowerSELECT from causing suboptimal codegen for __builtin_ffs(X) - 1. · 2328cab1
  Craig Topper authored Jun 08, 2020
  2328cab1
- [InstCombine] improve matching for sext-lshr-trunc patterns, part 2 · d50366d2
  Sanjay Patel authored Jun 08, 2020
  d50366d2
- [InstCombine] add tests for sext+lshr+trunc; NFC · 9b41821c
  Sanjay Patel authored Jun 08, 2020
  9b41821c
- [AArch64] Add a ldst-opt test with undef operands (NFC). · 22c2dc59
  Florian Hahn authored Jun 08, 2020
  22c2dc59
- AMDGPU/GlobalISel: Precommit regenerated check lines · 67b70048
  Matt Arsenault authored Jun 08, 2020
  67b70048
- [InstCombine] improve matching for sext-lshr-trunc patterns · 42f488b6
  Sanjay Patel authored Jun 08, 2020
  42f488b6
- [InstCombine] add tests for sext+lshr+trunc; NFC · 2e5bba67
  Sanjay Patel authored Jun 08, 2020
  2e5bba67
- [CodeGen] Fix nullptr crash in tryConvertSVEWideCompare · 41fb119e
  David Sherwood authored Jun 04, 2020
  41fb119e
- [VE] Support floating-point arithmetic instructions in MC layer · b60404a6
  Kazushi (Jam) Marukawa authored Jun 08, 2020
  b60404a6
- [AMDGPU] Cluster MIMG instructions · 275ecaae
  Jay Foad authored Feb 05, 2020
  275ecaae
- [AArch64][SVE] Implement vector tuple intrinsics · 3ebbe353
  Cullen Rhodes authored May 19, 2020
  3ebbe353
- Reverte AArch64 changes to popcount test, they break most bots. · 526352ba
  Nico Weber authored Jun 08, 2020
  526352ba
- [AArch64] Add combine-load test; NFC · 80ab9345
  Shawn Landden authored Jun 08, 2020
  80ab9345
- [VE] Support control instructions in MC layer · c95ba11a
  Kazushi (Jam) Marukawa authored Jun 08, 2020
  c95ba11a
- [CodeGen][SVE] CopyToReg: Split scalable EVTs that are not powers of 2 · ae09670e
  Sander de Smalen authored Jun 05, 2020
  ae09670e
- [AArch64] update popcount pre-patch test, take 2; NFC · 0fa3a033
  Shawn Landden authored Jun 08, 2020
  0fa3a033
- [AArch64] update popcount pre-patch test; NFC · 5787ad6c
  Shawn Landden authored Jun 08, 2020
  
  5787ad6c
- [NFC][PowerPC] Modify the test case to test RM · 47dff188
  Kang Zhang authored Jun 08, 2020
  
  47dff188
- [VE] Support shift operation instructions in MC layer · 385adc47
  Kazushi (Jam) Marukawa authored Jun 08, 2020
  385adc47
- [ARM][XO] Execute-only miscompiles double literals for big-endian · 7432fb2c
  Simon Wallis authored Jun 08, 2020
  7432fb2c
- [Test] Add test showing InstCombine missing simplification opportunity · 005db9c3
  Max Kazantsev authored Jun 08, 2020
  
  005db9c3
- [X86] Support load shrinking for strict fp nodes in combineCVTPH2PS · b0eea721
  Craig Topper authored Jun 07, 2020
  
  b0eea721
- [PowerPC] Do not assume operand of ADDI is an immediate · a56d057d
  Nemanja Ivanovic authored Jun 07, 2020
  a56d057d
- [X86] Improve (vzmovl (insert_subvector)) combine to handle a bitcast between the vzmovl and insert · e3aece06
  Craig Topper authored Jun 07, 2020
  e3aece06
- [X86] Teach combineCVTP2I_CVTTP2I to handle STRICT_CVTTP2SI/STRICT_CVTTP2UI · 22987bab
  Craig Topper authored Jun 07, 2020
  22987bab
- [Power9] Add addi post-ra scheduling heuristic · f8eabd6d
  QingShan Zhang authored Jun 08, 2020
  f8eabd6d