Commits · 2762da0a16a763654254e3320a3f46be2bb742b4 · Lorenzo Albano / LLVM bpEVL · GitLab

Jul 16, 2020
- [SVE][CodeGen] Legalisation of masked loads and stores · 2762da0a
  Kerry McLaughlin authored Jul 16, 2020
  2762da0a
- AMDGPU/GlobalISel: Select G_FREEZE · 5658002b
  Petar Avramovic authored Jul 16, 2020
  5658002b
- Revert "[NFCI] createCFGSimplificationPass(): migrate to also take SimplifyCFGOptions" · 1067d3e1
  Adrian Kuegel authored Jul 16, 2020
  1067d3e1
- Revert "[NFC] SimplifyCFGOptions: drop multi-parameter ctor, use default member-init" · 5831e861
  Adrian Kuegel authored Jul 16, 2020
  5831e861
- [X86] Allow lsl/lar to be parsed with a GR16, GR32, or GR64 as source register. · 71b49aa4
  Craig Topper authored Jul 15, 2020
  71b49aa4
- [PowerPC][Power10] Fix VINS* (vector insert byte/half/word) instructions to have i32 arguments. · fc553086
  Amy Kwan authored Jul 16, 2020
  fc553086
- [AMDGPU] Update VMEM scalar write hazard mitigation sequence · 5bf2a9dd
  Carl Ritson authored Jul 16, 2020
  5bf2a9dd
- [AMDGPU][CostModel] Improve cost estimation for fused {fadd|fsub}(a,fmul(b,c)) · 76a0c0ee
  dfukalov authored Jul 16, 2020
  76a0c0ee
- [NFC] SimplifyCFGOptions: drop multi-parameter ctor, use default member-init · 90c1b044
  Roman Lebedev authored Jul 16, 2020
  90c1b044
- [NFCI] createCFGSimplificationPass(): migrate to also take SimplifyCFGOptions · b2018198
  Roman Lebedev authored Jul 16, 2020
  b2018198
- [X86] Teach assembler parser to accept lsl and lar with a 64 or 32 source... · 3c2a56a8
  Craig Topper authored Jul 15, 2020
  3c2a56a8
Jul 15, 2020
- [AMDGPU][MC] Corrected MTBUF parsing and decoding · e122eba1
  Dmitry Preobrazhensky authored Jul 15, 2020
  e122eba1
- [mips] Rename FeatureMadd4 to FeatureNoMadd4. NFC · 3a6c2a61
  YunQiang Su authored Jul 15, 2020
  3a6c2a61
- [RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbt asm instructions · c9c955ad
  lewis-revill authored Jul 15, 2020
  c9c955ad
- [RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbs asm instructions · d4be3337
  lewis-revill authored Jul 15, 2020
  d4be3337
- [RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbbp asm instructions · 6144f0a1
  lewis-revill authored Jul 15, 2020
  6144f0a1
- [RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbp asm instructions · 31b52b43
  lewis-revill authored Jul 15, 2020
  31b52b43
- [RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbb asm instructions · e2692f0e
  lewis-revill authored Jul 15, 2020
  e2692f0e
- [RISCV] Duplicate pseudo expansion comment to RISCVMCCodeEmitter · 2dc16fbd
  Jessica Clarke authored Jul 15, 2020
  2dc16fbd
- [RISCV] Fix RISCVInstrInfo::getInstSizeInBytes for atomics pseudos · 3382c243
  Jessica Clarke authored Jul 15, 2020
  3382c243
- [AMDGPU] Apply pre-emit s_cbranch_vcc optimation to more patterns · 67422612
  Carl Ritson authored Jul 15, 2020
  67422612
Jul 14, 2020
- Call Frame Information (CFI) Handling for Basic Block Sections · c3e65556
  Krzysztof Pszeniczny authored Jul 14, 2020
  c3e65556
- [NFC] Add 'override' keyword where missing in include/ and lib/. · a19461d9
  Logan Smith authored Jul 14, 2020
  a19461d9
- [AMDGPU] Simplify AMDGPUSubtarget::getWavesPerEU. NFC. · 8a242089
  Jay Foad authored Jul 14, 2020
  
  8a242089
- [RISCV] Fix isStoreToStackSlot · 0cbdd2a8
  Roger Ferrer authored Jul 14, 2020
  0cbdd2a8
- Revert "[RISCV] Avoid Splitting MBB in RISCVExpandPseudo" · 1d15bbb9
  Sam Elliott authored Jul 14, 2020
  1d15bbb9
- [AArch64][AsmParser] Add rcpc support in .arch_extension · dad18687
  Victor Campos authored Jul 13, 2020
  dad18687
- [AMDGPU] Fix typos in performCtlz_CttzCombine() · 5ab2e14d
  Jay Foad authored Jul 14, 2020
  5ab2e14d
- [ARM][MVE] Only tail-fold integer add reductions · 959eaa50
  Sjoerd Meijer authored Jul 13, 2020
  959eaa50
- [AArch64][SVE] Remove erroneous assert in resolveFrameOffsetReference · a8f4f85d
  Sander de Smalen authored Jul 13, 2020
  a8f4f85d
- [AMDGPU] Avoid using s_cmpk when src0 is not register · 1658b8d7
  Jay Foad authored Jul 14, 2020
  1658b8d7
- [AMDGPU] Propagate dead flag during pre-RA exec mask optimizations · 74c14202
  Carl Ritson authored Jul 14, 2020
  74c14202
- [PowerPC][Power10] Implement Test LSB by Byte Builtins in LLVM/Clang · 62f5ba62
  Amy Kwan authored Jul 13, 2020
  62f5ba62
- [AArch64][GlobalISel] Add post-legalize combine for sext_inreg(trunc(sextload)) -> copy · 64eb3a49
  Amara Emerson authored Jun 17, 2020
  64eb3a49
- [PowerPC] Generate CFI directives when probing in prologue · d4e7d126
  Kai Luo authored Jul 13, 2020
  d4e7d126
- [PowerPC] Fix combineVectorShuffle regression after D77448 · eafe7c14
  Fangrui Song authored Jul 13, 2020
  eafe7c14
- Fold the opt size check into the assert to silence an unused variable warning. · e9583795
  Eric Christopher authored Jul 13, 2020
  
  e9583795
Jul 13, 2020
- GlobalISel: Implement widenScalar for saturating add/sub · 6a8c11a1
  Matt Arsenault authored Jul 12, 2020
  6a8c11a1
- Fix HexagonGenExtract return status · 62881fda
  serge-sans-paille authored Jul 09, 2020
  62881fda
- RISCV: Avoid GlobalISel build break in a future patch · db091e12
  Matt Arsenault authored Jul 13, 2020
  db091e12