This commit improves numerous functionalities of the OpenMP CMake build 
system to be more conducive with LLVM's build system and build philosophies.
The CMake build system, as it was before this commit, was not up to LLVM's 
standards and did not implement the configuration stage like most CMake based
build systems offer (check for compiler flags, libraries, etc.) In order to
improve it dramatically in a short period of time, a large refactoring had 
to be done.
The main changes done with this commit are as follows:

* Compiler flag checks - The flags are no longer grabbed from compiler specific
  directories.  They are checked for availability in config-ix.cmake and added
  accordingly inside LibompHandleFlags.cmake.
* Feature checks were added in config-ix.cmake.  For example, the standard CMake
  module FindThreads is probed for the threading model to use inside the OpenMP
  library.
* OS detection - There is no longer a LIBOMP_OS variable, OS-specifc build logic
  is wrapped around the WIN32 and APPLE macros with !(WIN32 OR APPLE) meaning 
  a Unix flavor of some sort.
* Got rid of vestigial functions/macros/variables
* Added new libomp_append() function which is used everywhere to conditionally
  or undconditionally append to a list
* All targets have the libomp prefix so as not to interfere with any other
  project
* LibompCheckLinkerFlag.cmake module was added which checks for linker flags
  specifically for building shared libraries.
* LibompCheckFortranFlag.cmake module was added which checks for fortran flag
  availability.
* Removed most of the cruft from the translation between the perl+Makefile based
  build system and this one.  The remaining components that they share are
  perl scripts which I'm in the process of removing.

There is still more left to do.  The perl scripts still need to be removed, and
a config.h.in file (or similarly named) needs to be added with #cmakedefine lines
in it.  But this is a much better first step than the previous system.

Differential Revision: http://reviews.llvm.org/D10656

llvm-svn: 242298

The vec_sld interface provides access to the vsldoi instruction.
Unlike most of the vec_* interfaces, we do not attempt to change the
generated code for vec_sld based on the endian mode.  It is too
difficult to correctly infer the desired semantics because of
different element types, and the corrected instruction sequence is
expensive, involving loading a permute control vector and performing a
generalized permute.

For GCC, this was implemented as "Don't touch the vec_sld"
implementation.  When it came time for the LLVM implementation, I did
the same thing.  However, this was hasty and incorrect.  In LLVM's
version of altivec.h, vec_sld was previously defined in terms of the
vec_perm interface.  Because vec_perm semantics are adjusted for
little endian, this means that leaving vec_sld untouched causes it to
generate something different for LE than for BE.  Not good.

This patch adjusts the form of vec_perm that is used for vec_sld and
vec_vsldoi, effectively undoing the modifications so that the same
vsldoi instruction will be generated for both BE and LE.

There is an accompanying back-end patch to take care of some small
ripple effects caused by these changes.

llvm-svn: 242297

The vec_sld interface provides access to the vsldoi instruction.
Unlike most of the vec_* interfaces, we do not attempt to change the
generated code for vec_sld based on the endian mode.  It is too
difficult to correctly infer the desired semantics because of
different element types, and the corrected instruction sequence is
expensive, involving loading a permute control vector and performing a
generalized permute.

For GCC, this was implemented as "Don't touch the vec_sld"
implementation.  When it came time for the LLVM implementation, I did
the same thing.  However, this was hasty and incorrect.  In LLVM's
version of altivec.h, vec_sld was previously defined in terms of the
vec_perm interface.  Because vec_perm semantics are adjusted for
little endian, this means that leaving vec_sld untouched causes it to
generate something different for LE than for BE.  Not good.

This back-end patch accompanies the changes to altivec.h that change
vec_sld's behavior for little endian.  Those changes mean that we see
slightly different code in the back end when trying to recognize a
VSLDOI instruction in isVSLDOIShuffleMask.  In particular, a
ShuffleKind of 1 (where the two inputs are identical) must now be
treated the same way as a ShuffleKind of 2 (little endian with
different inputs) when little endian mode is in force.  This is
because ShuffleKind of 1 is defined using big-endian numbering.

This has a ripple effect on LowerBUILD_VECTOR, where we create our own
internal VSLDOI instructions.  Because these are a ShuffleKind of 1,
they will now have their shift amounts subtracted from 16 when
recognizing the shuffle mask.  To avoid problems we have to subtract
them from 16 again before creating the VSLDOI instructions.

There are a couple of other uses of BuildVSLDOI, but these do not need
to be modified because the shift amount is 8, which is unchanged when
subtracted from 16.

llvm-svn: 242296

- Teaches the ValueTracker in the PeepholeOptimizer to look through PHI
instructions.
- Add findNextSourceAndRewritePHI method to lookup into multiple sources
returnted by the ValueTracker and rewrite PHIs with new sources.

With these changes we can find more register sources and rewrite more
copies to allow coaslescing of bitcast instructions. Hence, we eliminate
unnecessary VR64 <-> GR64 copies in x86, but it could be extended to
other archs by marking "isBitcast" on target specific instructions. The
x86 example follows:

A:
  psllq %mm1, %mm0
  movd  %mm0, %r9
  jmp C

B:
  por %mm1, %mm0
  movd  %mm0, %r9
  jmp C

C:
  movd  %r9, %mm0
  pshufw  $238, %mm0, %mm0

Becomes:

A:
  psllq %mm1, %mm0
  jmp C

B:
  por %mm1, %mm0
  jmp C

C:
  pshufw  $238, %mm0, %mm0

Differential Revision: http://reviews.llvm.org/D11197

rdar://problem/20404526

llvm-svn: 242295

- Create a new CopyRewriter for Uncoalescable copy-like instructions
- Change the ValueTracker to return a ValueTrackerResult

This makes optimizeUncoalescable looks more like optimizeCoalescable and
use the CopyRewritter infrastructure.

This is also the preparation for looking up into PHI nodes in the
ValueTracker.

Differential Revision: http://reviews.llvm.org/D11195

llvm-svn: 242294

Fixes pr24130.

llvm-svn: 242293

http://reviews.llvm.org/D11071

Patch by Martell Malone
Reviewed by Reid Kleckner

llvm-svn: 242292

Summary:
libtool_VERSION was changed in gofrontend a while ago,
but CMakeLists.txt in llgo wasn't updated, and so the
install target fails. Not sure how this went unnoticed
for so long.

Reviewers: pcc

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11118

llvm-svn: 242291

Summary:
If a function requires a landing pad, set the personality function.

Requires D11116.

Reviewers: pcc

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11117

llvm-svn: 242290

Summary:
Add Value.SetPersonality to the Go bindings. The Go
bindings' Builder.CreateLandingPad has been updated,
removing the obsolete personality argument.

Background

The personality attribute was removed from LandingPadInst
in r239940, and llvm::Function::setPersonalityFn introduced.

There was no corresponding change to either the C API or
Go bindings. The Go bindings were broken until r239940, but
that change was just to ignore the personality argument.
This broke llgo.

Reviewers: majnemer, pcc

Subscribers: deadalnix, llvm-commits, axw

Differential Revision: http://reviews.llvm.org/D11116

llvm-svn: 242289

PR24122. The test is simply a byte swapped version of ppc64-encoding.txt.

llvm-svn: 242288

Differential Revision: http://reviews.llvm.org/D11095

llvm-svn: 242287

We now use the sanitizer special case list to decide which types to blacklist.
We also support a special blacklist entry for types with a uuid attribute,
which are generally COM types whose virtual tables are defined externally.

Differential Revision: http://reviews.llvm.org/D11096

llvm-svn: 242286

[OPENMP] http://llvm.org/PR24121: canonical loop rejected when comparison has implicit conversions or destruction

Allow to use complex iterators expressions in loops for C++.

llvm-svn: 242285

-Implemented as a table lookup.

Change-Id: Iaad0eaf4b29b06827e6700269496dc1ba20e9018
Phabricator: http://reviews.llvm.org/D11100
llvm-svn: 242284

Thanks to Alexpux.

llvm-svn: 242283

llvm-svn: 242282

inspection.

While we want to handle calls specially in this code because they should
have been modeled by the call graph analysis that precedes it, we should
*not* be re-implementing the predicates for whether an instruction reads
or writes memory. Those are well defined already. Notably, at least the
following issues seem to be clearly missed before:
- Ordered atomic loads can "write" to memory by causing writes from other
  threads to become visible. Similarly for ordered atomic stores.
- AtomicRMW instructions quite obviously both read and write to memory.
- AtomicCmpXchg instructions also read and write to memory.
- Fences read and write to memory.
- Invokes of intrinsics or memory allocation functions.

I don't have any test cases, and I suspect this has never really come up
in the real world. But there is no reason why it wouldn't, and it makes
the code simpler to do this the right way.

While here, I've tried to make the loops significantly simpler as well
and added helpful comments as to what is going on.

llvm-svn: 242281

Current implementation handles unordered comparison poorly in soft-float mode. 
Consider (a ULE b) which is a <= b. It is lowered to (ledf2(a, b) <= 0 || unorddf2(a, b) != 0) (in general). We can do better job by lowering it to (__gtdf2(a, b) <= 0). 
Such replacement is true for other CMP's (ult, ugt, uge). In general, we just call same function as for ordered case but negate comparison against zero.
Differential Revision: http://reviews.llvm.org/D10804

llvm-svn: 242280

This is a direct port of the code from the X86 backend (r239486/r240361), which
uses the MachineCombiner to reassociate (floating-point) adds/muls to increase
ILP, to the PowerPC backend. The rationale is the same.

There is a lot of copy-and-paste here between the X86 code and the PowerPC
code, and we should extract at least some of this into CodeGen somewhere.
However, I don't want to do that until this code is enhanced to handle FMAs as
well. After that, we'll be in a better position to extract the common parts.

llvm-svn: 242279

If the source of the copy that defines the addend is a physical register, then
its existing live range may not extend to the FMA being mutated. Make sure we
extend the live range of the register to meet the FMA because it will become
its operand in this case.

I don't have an independent test case, but it will be exposed by change to be
committed shortly enabling the use of the machine combiner to do fadd/fmul
reassociation, and will be covered by one of the associated regression tests.

llvm-svn: 242278

MachineCombiner predicated its use of scheduling-based metrics on
hasInstrSchedModel(), but useful conclusions can be drawn from pipeline
itineraries as well. Almost all of the logic (except for resource tracking in
preservesResourceLen) can be used if we have an itinerary, so enable it in that
case as well.

This will be used by the PowerPC backend in an upcoming commit.

llvm-svn: 242277

Bitpatterns rejected by the decoder method of `MSR (immediate)` should be
decoded as the `extended MSR (register)` instruction.

Differential Revision: http://reviews.llvm.org/D7174

llvm-svn: 242276

llvm-svn: 242275

When FixedLenDecoder matches an input bitpattern of form [01]+ with an
instruction bitpattern of form [01?]+ (where 0/1 are static bits and ? are
mixed/variable bits) it passes the input bitpattern to a specific instruction
decoder method which then makes a final decision whether the bitpattern is a
valid instruction or not. This means the decoder must handle all possible
values of the variable bits which sometimes leads to opcode rewrites in the
decoder method when the instructions are not fully orthogonal.

The patch provides a way for the decoder method to say that when it returns
Fail it does not necessarily mean the bitpattern is invalid, but rather that
the bitpattern is definitely not an instruction that is recognized by the
decoder method. The decoder can then try to match the input bitpattern with
other possible instruction bitpatterns.

For example, this allows to solve a situation on AArch64 where the `MSR
(immediate)` instruction has form:
1101 0101 0000 0??? 0100 ???? ???1 1111
but not all values of the ? bits are allowed. The rejected values should be
handled by the `extended MSR (register)` instruction:
1101 0101 000? ???? ???? ???? ???? ????

The decoder will first try to decode an input bitpattern that matches both
bitpatterns as `MSR (immediate)` but currently this puts the decoder method of
`MSR (immediate)` into a situation when it must be able to decode all possible
values of the ? bits, i.e. it would need to rewrite the instruction to `MSR
(register)` when it is not `MSR (immediate)`.

The patch allows to specify that the decoder method cannot determine if the
instruction is valid for all variable values. The decoder method can simply
return Fail when it knows it is definitely not `MSR (immediate)`. The decoder
will then backtrack the decoding and find that it can match the input
bitpattern with the more generic `MSR (register)` bitpattern too.

Differential Revision: http://reviews.llvm.org/D7174

llvm-svn: 242274

We were only testing on x86-64, but we should be ensuring decent code gen of i64 shifts on 32-bit targets.

llvm-svn: 242273

llvm-svn: 242272

llvm-svn: 242271

AVX : Fix ISA disabling in case AVX512VL , some instructions should be disabled only if AVX512BW present.
Tests added.

Differential Revision: http://reviews.llvm.org/D11122

llvm-svn: 242270

llvm-svn: 242269

llvm-svn: 242268

dejagnu.

I wonder if it would be useful to handle FileCheck prefixes specially?
Especially if we could get some error checking. Suggestions welcome.
Patches more welcome as I have no idea what I'm doing with vim
script....

llvm-svn: 242267

to intelligently wrap prose written in IR comment blocks. This has
bothered me for roughly ever, and my fellow IRC denziens convinced me to
fix it.

llvm-svn: 242266

The unsigned opcode argument here was the result of BinaryOperator->getOpcode().
That returns a BinaryOps enum which is more accurate than passing around an
unsigned.

llvm-svn: 242265

This code was checking if we are an ICmpInst or FCmpInst then throwing
unreachable if we are neither.  We must be one or the other, so use a
cast on the FCmpInst case to ensure that we are that case.  Then we can
avoid having an unreachable but still catch an error if we ever had another
subclass of CmpInst.

llvm-svn: 242264

llvm-svn: 242263

both for packet success and that the response is OK.

llvm-svn: 242262

The code here was doing exactly what is already in getAnyExtOrTrunc().
Just use that method instead.

llvm-svn: 242261

The code here was doing exactly what is already in getZExtOrTrunc().
Just use that method instead.

llvm-svn: 242260

Because thunks for dllimported symbols contain absolute addresses on x86,
they need to be relocated at load-time. This bug was a cause of crashes
in DLL initialization routines.

llvm-svn: 242259