Commits · 36d4092173179b25b931a522361cf6139a7c635a · Lorenzo Albano / LLVM bpEVL · GitLab

Dec 20, 2018
- AMDGPU/GlobalISel: Legality/regbankselect for atomicrmw/atomic_cmpxchg · 36d40921
  Matt Arsenault authored Dec 20, 2018
  36d40921
- [X86] Remove TLI variable from ReplaceNodeResults. NFC · 217b3b20
  Craig Topper authored Dec 19, 2018
  217b3b20
Dec 19, 2018
- AMDGPU: Add patterns for v4i16/v4f16 -> v4i16/v4f16 bitcasts · 3931ad38
  Rhys Perry authored Dec 19, 2018
  3931ad38
- [AArch64] Improve Exynos predicates · 374ccf67
  Evandro Menezes authored Dec 19, 2018
  374ccf67
- [AArch64] Use canonical copy idiom · ff827d73
  Evandro Menezes authored Dec 19, 2018
  ff827d73
- [X86] Remove a bunch of 'else' after returns in reduceVMULWidth. NFC · d16da2b4
  Craig Topper authored Dec 19, 2018
  d16da2b4
- [GlobalISel][AArch64] Add support for @llvm.ceil · 3560e93d
  Jessica Paquette authored Dec 19, 2018
  3560e93d
- [X86] Don't match TESTrr from (cmp (and X, Y), 0) during isel. Defer to post processing · 84a00bd9
  Craig Topper authored Dec 19, 2018
  84a00bd9
- [X86] Fix assert fails in pass X86AvoidSFBPass · 29147034
  Craig Topper authored Dec 19, 2018
  29147034
- [AArch64] Improve the Exynos M3 pipeline model · 5d409b22
  Evandro Menezes authored Dec 19, 2018
  5d409b22
- [BPF] Generate BTF DebugInfo under BPF target · 7b410ac3
  Yonghong Song authored Dec 19, 2018
  7b410ac3
- AMDGPU: Use an ABS32_LO relocation for SCRATCH_RSRC_DWORD1 · 8d5e9740
  Nicolai Haehnle authored Dec 19, 2018
  8d5e9740
- AMDGPU/InsertWaitcnts: Update VGPR/SGPR bounds when brackets are merged · c521ac3a
  Carl Ritson authored Dec 19, 2018
  c521ac3a
- [ARM GlobalISel] Support G_CONSTANT for Thumb2 · 6c35a1e5
  Diana Picus authored Dec 19, 2018
  6c35a1e5
- AMDGPU/GlobalISel: Regbankselect for fsub · b110e227
  Matt Arsenault authored Dec 19, 2018
  b110e227
- [PowerPC]Exploit P9 vabsdu for unsigned vselect patterns · a6247e7c
  Kewen Lin authored Dec 19, 2018
  a6247e7c
- [AArch64] Simplify the Exynos M3 pipeline model · f03c45d5
  Evandro Menezes authored Dec 18, 2018
  f03c45d5
- [AArch64] Fix instructions order (NFC) · 4e39fa44
  Evandro Menezes authored Dec 18, 2018
  4e39fa44
Dec 18, 2018
- [X86] Add BSR to isUseDefConvertible. · 18a9d545
  Craig Topper authored Dec 18, 2018
  18a9d545
- [AMDGPU] Removed the unnecessary operand size-check-assert from processBaseWithConstOffset(). · 59ee2c53
  Farhana Aleen authored Dec 18, 2018
  59ee2c53
- [X86] Don't use SplitOpsAndApply to create ISD::UADDSAT/ISD::USUBSAT nodes.... · 8434ef7d
  Craig Topper authored Dec 18, 2018
  8434ef7d
- [X86] Use SADDSAT/SSUBSAT instead of ADDS/SUBS · f6058ff1
  Nikita Popov authored Dec 18, 2018
  f6058ff1
- [X86] Create PSUBUS from (add (umax X, C), -C) · 20a6db5a
  Craig Topper authored Dec 18, 2018
  20a6db5a
- [X86][SSE] Don't use 'sign bit select' vXi8 ROTL lowering for constant rotation amounts · 14119174
  Simon Pilgrim authored Dec 18, 2018
  14119174
- [X86][SSE] Don't use 'sign bit select' vXi8 ROTL lowering for splat rotation amounts · e9effe97
  Simon Pilgrim authored Dec 18, 2018
  e9effe97
- [MIPS GlobalISel] Select G_SDIV, G_UDIV, G_SREM and G_UREM · 0a5e4eb7
  Petar Avramovic authored Dec 18, 2018
  0a5e4eb7
- [X86] Use UADDSAT/USUBSAT instead of ADDUS/SUBUS · 665ab081
  Nikita Popov authored Dec 18, 2018
  665ab081
- [MIPS GlobalISel] ClampScalar G_AND G_OR and G_XOR · 150fd430
  Petar Avramovic authored Dec 18, 2018
  150fd430
- [AArch64] - Return address signing dwarf support · f57d7d82
  Luke Cheeseman authored Dec 18, 2018
  f57d7d82
- AMDGPU: Legalize/regbankselect frame_index · c94e26c7
  Matt Arsenault authored Dec 18, 2018
  c94e26c7
- AMDGPU: Legalize/regbankselect fma · c0ea2210
  Matt Arsenault authored Dec 18, 2018
  c0ea2210
- AMDGPU/GlobalISel: Legalize/regbankselect fneg/fabs/fsub · e01e7c81
  Matt Arsenault authored Dec 18, 2018
  e01e7c81
- [X86][SSE] Move VSRAI sign extend in reg fold into SimplifyDemandedBits · 8488a44c
  Simon Pilgrim authored Dec 18, 2018
  8488a44c
- [X86][SSE] Replace (VSRLI (VSRAI X, Y), 31) -> (VSRLI X, 31) fold. · 26c630f4
  Simon Pilgrim authored Dec 18, 2018
  26c630f4
- Introduce control flow speculation tracking pass for AArch64 · e66bc1f7
  Kristof Beyls authored Dec 18, 2018
  e66bc1f7
- [AArch64] [MinGW] Allow enabling SEH exceptions · 8f0cb9c3
  Martin Storsjö authored Dec 18, 2018
  8f0cb9c3
- [PowerPC] Exploit power9 new instruction setb · 44ace925
  Kewen Lin authored Dec 18, 2018
  44ace925
- [X86] Const correct some helper functions X86InstrInfo.cpp. NFC · 1ff7356f
  Craig Topper authored Dec 18, 2018
  1ff7356f
- [PowerPC] Improve vec_abs on P9 · 3dac1252
  Kewen Lin authored Dec 18, 2018
  3dac1252
Dec 17, 2018
- [X86][SSE] Improve immediate vector shift known bits handling. · 7e2975a4
  Simon Pilgrim authored Dec 17, 2018
  7e2975a4