Commits · 4391d764e153d17315a2822137e1ceca13b4c98d · Lorenzo Albano / LLVM bpEVL · GitLab

Apr 01, 2021
- [ARM] Remove an unused parameter in ARMWinCOFFObjectWriter. NFC. · 4391d764
  Martin Storsjö authored Mar 30, 2021
  4391d764
- [MC][ARM] add .w suffixes for RSB/RSBS T1 · 52338af5
  Nick Desaulniers authored Apr 01, 2021
  52338af5
- [RISCV] Fix handling of nxvXi64 vmsgt(u).vx intrinsics on RV32. · d157e3f3
  Craig Topper authored Apr 01, 2021
  d157e3f3
- [MC][ARM] add .w suffixes for ORN/ORNS T1 · 1addc231
  Nick Desaulniers authored Apr 01, 2021
  1addc231
- [RISCV] Add custom type legalization to form MULHSU when possible. · b7c2e577
  Craig Topper authored Apr 01, 2021
  b7c2e577
- [AMDGPU] Remove SIAddIMGInit pass which is now unused · fdc4f19e
  Jay Foad authored Apr 01, 2021
  fdc4f19e
- [AMDGPU][GlobalISel] Add IMG init in selectImageIntrinsic · 3d07a6d8
  Jay Foad authored Mar 31, 2021
  3d07a6d8
- [AMDGPU][SDag] Add IMG init in AdjustInstrPostInstrSelection · 4af6251c
  Jay Foad authored Apr 01, 2021
  4af6251c
- [RISCV] Improve 64-bit integer materialization for some cases. · d61b40ed
  Craig Topper authored Apr 01, 2021
  d61b40ed
- [AMDGPU] Small cleanup to constructRetValue and its caller. NFC. · b1fbfd9e
  Jay Foad authored Apr 01, 2021
  
  b1fbfd9e
- [regalloc] Ensure Query::collectInterferringVregs is called before interval iteration · ce61def5
  Mircea Trofin authored Mar 08, 2021
  ce61def5
- [AArch64][SVE] Improve codegen for select nodes with fixed types · 2f45e632
  Bradley Smith authored Mar 25, 2021
  2f45e632
- [AArch64][SVE] SVE functions should use the SVE calling convention for fast calls · 0934fa4f
  Bradley Smith authored Mar 30, 2021
  0934fa4f
- [AMDGPU] Enable output modifiers for double precision instructions · 65c8bfb5
  Brendon Cahoon authored Mar 25, 2021
  65c8bfb5
- [AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 suffices · cd953434
  Dmitry Preobrazhensky authored Apr 01, 2021
  cd953434
- [X86][SSE] Fold HOP(HOP(X,X),HOP(Y,Y)) -> HOP(PERMUTE(HOP(X,Y)),PERMUTE(HOP(X,Y)) · abbe80fa
  Simon Pilgrim authored Apr 01, 2021
  abbe80fa
- [X86][SSE] Enable (F)HADD/SUB handling to SimplifyMultipleUseDemandedVectorElts · 30131984
  Simon Pilgrim authored Mar 31, 2021
  30131984
- [X86][SSE] Add isHorizOp helper function. NFCI. · f7aeaced
  Simon Pilgrim authored Mar 31, 2021
  
  f7aeaced
- [AMDGPU][MC] Added flag to identify VOP instructions which have a single variant · 0f5ebbcc
  Dmitry Preobrazhensky authored Apr 01, 2021
  0f5ebbcc
- [WebAssembly] Invert branch condition on xor input · 92e77714
  Sam Parker authored Mar 31, 2021
  92e77714
- [RISCV] Add UnsupportedSchedZfh multiclass to reduce duplicate lines from... · c88ee1a0
  Craig Topper authored Mar 31, 2021
  c88ee1a0
Mar 31, 2021
- [X86] add dwarf annotation for inline stack probe · 1c268a8f
  YangKeao authored Mar 31, 2021
  1c268a8f
- [WebAssembly] Implement i64x2 comparisons · 45783d0e
  Thomas Lively authored Mar 31, 2021
  45783d0e
- [X86] Improve SMULO/UMULO codegen for vXi8 vectors. · 437958d9
  Craig Topper authored Mar 31, 2021
  437958d9
- [PowerPC] [MLICM] Enable hoisting of caller preserved registers on AIX · 00c0c8c8
  Shimin Cui authored Mar 31, 2021
  00c0c8c8
- [X86] Improve optimizeCompareInstr for signed comparisons after BMI/TBM instructions · 50b8634a
  Craig Topper authored Mar 31, 2021
  50b8634a
- [RISCV] Add RISCVISD opcodes for CLZW and CTZW. · 2a8b7cab
  Craig Topper authored Mar 31, 2021
  2a8b7cab
- [RISCV] Add isel patterns to select vsub_vx intrinsic to vadd.vi if it uses a... · 04f10ab3
  Craig Topper authored Mar 31, 2021
  04f10ab3
- [SVE] Fix LoopVectorizer test scalalable-call.ll · 7108b2de
  Sander de Smalen authored Feb 23, 2021
  7108b2de
- NFC: Change getIntrinsicInstrCost to return InstructionCost · 2f6f249a
  Sander de Smalen authored Jan 22, 2021
  2f6f249a
- NFC: Change getTypeBasedIntrinsicCost to return InstructionCost · 2f56e1c6
  Sander de Smalen authored Jan 22, 2021
  2f56e1c6
- [X86] AMD Zen 3 has macro fusion · ce548aa2
  Roman Lebedev authored Mar 31, 2021
  ce548aa2
- [RISCV] Add support for the stepvector intrinsic · 10fc6e43
  Fraser Cormack authored Mar 30, 2021
  10fc6e43
- [AMDGPU][GlobalISel] Add support for global atomicrmw fadd · 5d0e9ddf
  Jay Foad authored Mar 01, 2021
  5d0e9ddf
- [AArch64] Avoid SCALAR_TO_VECTOR for single FP constant vector. · 52e01508
  Florian Hahn authored Mar 31, 2021
  52e01508
- NFC: Change getUserCost to return InstructionCost · 3ccbd4f3
  Sander de Smalen authored Jan 20, 2021
  3ccbd4f3
- [RISCV] simm12_plus1 should not inherit from Operand. NFC · 5db19cc0
  Craig Topper authored Mar 30, 2021
  5db19cc0
- [RISCV] Remove some unused ImmLeafs. NFC · 05998701
  Craig Topper authored Mar 30, 2021
  05998701
Mar 30, 2021
- [ARM] Add FeatureHasNoBranchPredictor for Thumb1 cores · 3a6365a4
  David Green authored Mar 30, 2021
  3a6365a4
- [GlobalISel] Fix -Wunused-variable in -DLLVM_ENABLE_ASSERTIONS=off builds after D99463 · 73adc05c
  Fangrui Song authored Mar 30, 2021
  
  73adc05c