llvm-svn: 135533

The system register spec should be case insensitive. The preferred form for
output with mask values of 4, 8, and 12 references APSR rather than CPSR.
Update and tidy up tests accordingly.

llvm-svn: 135532

llvm-svn: 135528

Teach the parser to recognize the APSR and SPSR system register names. Add
and update tests accordingly.

llvm-svn: 135527

llvm-svn: 135524

llvm-svn: 135522

Add range checking to the immediate operands. Update tests accordingly.

llvm-svn: 135521

ANDi, when the instruction does not have any immediate operands.

llvm-svn: 135520

llvm-svn: 135517

llvm-svn: 135516

llvm-svn: 135514

Correct the handling of the 's' suffix when parsing ARM mode. It's only a
truly separate opcode in Thumb. Add test cases to make sure we handle
the s and condition suffices correctly, including diagnostics.

llvm-svn: 135513

llvm-svn: 135507

Make sure we only clobber the cc_out operand if it is indeed a default
non-setting operand.

llvm-svn: 135506

llvm-svn: 135504

Add range checking for the immediate operand and handle the "mov" mnemonic
choosing between encodings based on the value of the immediate. Add tests
for fixups, encoding choice and values, and diagnostic for out of range values.

llvm-svn: 135500

llvm-svn: 135499

cc_out and pred operands are added during parsing via custom C++ now.

llvm-svn: 135497

llvm-svn: 135496

- In EmitAtomicBinaryPartword, mask incr in loopMBB only if atomic.swap is the
  instruction being expanded, instead of masking it in thisMBB. 
- Remove redundant Or in EmitAtomicCmpSwap. 

llvm-svn: 135495

basic blocks.

llvm-svn: 135490

llvm-svn: 135489

Revert "Make a provision to encode inline location in a variable. This will enable dwarf writer to easily distinguish between two instances of a inlined variable in one basic block."

This reverts commit 9fec5e346efdf744b151ae6604f912908315fa7a.

llvm-svn: 135486

This reverts commit ba034c0a2e71303c7cf3f43ca8e69dc8436b32e2.

llvm-svn: 135485

llvm-svn: 135483

llvm-svn: 135482

llvm-svn: 135481

llvm-svn: 135478

llvm-svn: 135477

llvm-svn: 135476

llvm-svn: 135475

llvm-svn: 135474

to perform a signed wrap. Don't rely on any particular handling of that case.

llvm-svn: 135471

(including compilation, assembly). Move relocation model Reloc::Model from
TargetMachine to MCCodeGenInfo so it's accessible even without TargetMachine.

llvm-svn: 135468

ExpandISelPseudos::runOnMachineFunction does not visit instructions that have
just been added.

llvm-svn: 135465

llvm-svn: 135464

Make isLoadExtLegal and isTruncStoreLegal check what the name says. :)  This might have some minor effect on CellSPU, but all other targets should be unaffected.  Fixing per report from Damien Vincent on llvmdev.

llvm-svn: 135462

llvm-svn: 135458

Make a provision to encode inline location in a variable. This will enable dwarf writer to easily distinguish between two instances of a inlined variable in one basic block.

llvm-svn: 135457

Revert r135423.

llvm-svn: 135454